Electrical computers and digital processing systems: processing – Instruction decoding – Decoding by plural parallel decoders
Patent
1997-07-25
1999-10-05
An, Meng-Ai T.
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding by plural parallel decoders
712 11, 712200, 712203, 712206, 712208, 712209, 712210, 712213, 712215, 712235, G06F 900
Patent
active
059616326
ABSTRACT:
A processor processes a plurality of instructions according to a disclosed method. First, the method receives (32) an instruction from the plurality of instructions. Second, the method determines (34) whether the received instruction is preceded by an instruction path leading code. Third, the method passes (36 or 38) the received instruction along at least one instruction path in a plurality of instruction paths. Fourth, in response to determining that the received instruction is preceded by an instruction path leading code, the method executes a machine word corresponding to the received instruction and selected from one of the plurality of instruction paths. Specifically, the selected instruction path is selected in response to the instruction path leading code.
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Shiell Jonathan H.
Steiss Donald E.
An Meng-Ai T.
Donaldson Richard L.
Laws Gerald E.
Marshall, Jr. Robert D.
Nguyen Dzung C
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