Microprocessor with circuits, systems, and methods for interrupt

Details Microprocessor with circuits, systems, and methods for interrupt Microprocessor with circuits, systems, and methods for interrupt

1997-03-25

1999-10-26

Toplu, Lucien U.

Electrical computers and digital processing systems: multicomput

Computer-to-computer data routing

Least weight routing

709100, G06F 1200

Patent

active

059744405

ABSTRACT:
In a microprocessor embodiment (26), the microprocessor is operable to multi-task a plurality of programs, wherein the plurality of programs include a virtual program (38, 40) operable in a virtual mode and a monitor program (36) in a protected mode. The microprocessor includes an interrupt handling circuit (30) for executing an interrupt handler in response to a hardware interrupt request signal (HIM.cndot.INTR). The microprocessor further includes an interrupt flag bit (IF) set in a like manner in both the virtual mode and the protected mode. The interrupt flag bit is set in a first state to inhibit receipt of the hardware interrupt request signal by the interrupt handling circuit, and the interrupt flag bit is set in a second state to enable receipt of the hardware interrupt request signal by the interrupt handling circuit. The microprocessor further includes a virtual mode control signal (VM.cndot.VME), wherein the virtual mode control signal is set in a first state to indicate a program is operating in a virtual mode and is set in a second state to indicate a program is not operating in a virtual mode. Still further, the microprocessor includes a mask bit (HIM) and circuitry (46) for copying the state of the interrupt flag bit to the mask bit when the virtual mode control signal is set in the second state. The copying circuitry does not copy in this manner when the virtual mode control signal is set in the first state. Still further, the microprocessor includes circuitry (INTR) for receiving an external interrupt request signal, and logic circuitry (52) for presenting the hardware interrupt request to said interrupt handling circuit in response to a combination of the external interrupt request signal and the mask bit.

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patent: 5381540 (1995-01-01), Adams et al.
patent: 5644755 (1997-07-01), Wooten
patent: 5694606 (1997-12-01), Pletcher et al.
patent: 5729760 (1998-03-01), Poisner
patent: 5784625 (1998-07-01), Walker

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