Microprocessor with cache memory for supporting debugging operat

Details Microprocessor with cache memory for supporting debugging operat Microprocessor with cache memory for supporting debugging operat

1991-02-27

1994-05-17

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG1, G06F 1332

Patent

active

053136080

ABSTRACT:
A microprocessor consists of an arithmetic section for executing arithmetic processing with a program, a holding circuit for holding a designated address AD1 at which a piece of data DA1 is stored in an external memory, and a signal generating circuit for generating a signal when the designated address AD1 transmitted from the arithmetic section to the external memory is detected. The arithmetic section is provided with a cache memory for storing pieces of data, a tag memory for storing addresses at which the pieces of data are stored in the cache memory, a writing circuit for tagging the designated address AD1 stored in the tag memory after receiving the signal generated in the signal generating circuit, an arithmetic unit for executing arithmetic processing with the data stored in the cache memory, a brake signal generating circuit for generating a brake signal when the data DA1 stored at the designated address AD1 tagged is accessed by the arithmetic unit, and a control section for braking arithmetic processing executed in the arithmetic unit at a designated step of the program when the brake signal is provided from the circuit. The program used in the arithmetic unit is debugged after the arithmetic processing is braked.

REFERENCES:
patent: 4527236 (1985-07-01), Ermolovich
patent: 4635193 (1987-01-01), Moyer et al.
patent: 4791550 (1988-12-01), Stevenson et al.
patent: 4802085 (1989-01-01), Levy et al.
patent: 4860195 (1989-08-01), Krauskopf
patent: 5053949 (1991-10-01), Allison et al.

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