Microprocessor with cache memory

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Details

395250, 364956, 3649642, 364253, 3642434, G06F 1204, G06F 1300

Patent

active

053012968

ABSTRACT:
A microprocessor which has a plurality of cache memory units with plural ways, a plurality of data buses each having different bus width, and a write way control unit or an address control unit whichever capable of switching the number of ways or entries of these cache memory units in accordance with a bus mode determined by a specified data bus and accessing specific cache memory units, where by switching the number of ways or entries in accordance with the set bus mode the byte number of fetched instructions and data is brought into perfect accord with the data width (line size) of respective cache memory units during any bus mode. This in turn fully eliminates unused region of respective cache memory units to provide the improved efficiency of the use of the entire cache memory units.

REFERENCES:
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patent: 4445177 (1984-04-01), Bratt
patent: 4502110 (1985-02-01), Saito
patent: 4736293 (1988-04-01), Patrick
patent: 4802085 (1989-01-01), Levy
patent: 4905188 (1990-02-01), Chuang
patent: 4953073 (1990-08-01), Moussouris
patent: 5014195 (1991-05-01), Farrell
patent: 5113506 (1992-05-01), Moussouris
patent: 5119485 (1992-06-01), Ledbetter
patent: 5197144 (1993-03-01), Edenfield
patent: 5226130 (1993-07-01), Favor
patent: 5228134 (1993-07-01), MacWilliams
CMOS Design for Super LSI, 1986, p. 181 FIG. 5.29.

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