Boots – shoes – and leggings
Patent
1995-02-10
1995-12-12
Black, Thomas G.
Boots, shoes, and leggings
395800, 3642292, 36423221, 3642318, 364DIG1, G06F 928
Patent
active
054758246
ABSTRACT:
A computer system includes a dual instruction decoder which issues two instructions in parallel within a single clock cycle if their are no register dependencies between the instructions, and instructions fall within a predetermined subset of the complete instruction set. The system includes first and second instruction pipelines. The first pipeline executes any instruction issued from the full instruction set, while the second pipeline only executes a predetermined subset of instructions selected based on principles of locality. A register dependency checker determines whether the destination register of a first instruction is used during the execution of a second instruction in an instruction sequence. When both instructions are within the subset and there are no dependencies, the first and second instructions can be issued in parallel in the first and second pipelines.
REFERENCES:
patent: 4197579 (1980-04-01), Otis, Jr. et al.
patent: 4236206 (1980-11-01), Strecker et al.
patent: 4270181 (1981-05-01), Tamakura et al.
patent: 4424563 (1984-01-01), Lynch
patent: 4502111 (1985-02-01), Riffe et al.
patent: 4530050 (1985-07-01), Fukunaga et al.
patent: 4532589 (1985-07-01), Shintani et al.
patent: 4670890 (1987-06-01), Titchener
patent: 4714994 (1987-12-01), Oklobdzija et al.
patent: 4766566 (1988-08-01), Chuang
patent: 4811214 (1989-03-01), Nosenchuck et al.
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 4885680 (1989-12-01), Anthony et al.
patent: 5067069 (1991-11-01), Fite et al.
patent: 5072449 (1991-12-01), Enns et al.
patent: 5073855 (1991-12-01), Staplin et al.
patent: 5075840 (1991-12-01), Grohoski et al.
patent: 5075844 (1991-12-01), Jardine et al.
patent: 5113515 (1992-05-01), Fite et al.
patent: 5133077 (1992-07-01), Karne et al.
patent: 5148271 (1992-09-01), Kato et al.
patent: 5167026 (1992-11-01), Murray et al.
patent: 5179680 (1993-01-01), Colwell et al.
patent: 5201057 (1993-04-01), Uht
patent: 5202967 (1993-04-01), Matsuzaki et al.
patent: 5202972 (1993-04-01), Gusefski et al.
patent: 5226166 (1993-07-01), Ishida et al.
patent: 5233694 (1993-08-01), Hotta et al.
patent: 5241636 (1993-08-01), Kohn
patent: 5355460 (1994-10-01), Eickemeyer et al.
Fu et al., "Performance and Microarchitecture of the i486.TM. Processor," Proceedings of 1989 IEEE International Conference on Computers Design: VLSI in Computers and Processors, 1989, pp. 182-187.
Nakajima, et al.; "Ohmega: A VLSI Superscalar Processor Architecture for Numerical Applications"; Proceedings: The 18th Annual International Symposium on Computer Architecture; May 27-30, 1991; pp. 160-168.
Alpert Donald B.
Grochowski Edward T.
Shoemaker Kenneth D.
Zaidi Ahmad
Black Thomas G.
Ellcessor Larry J.
Intel Corporation
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