Microprocessor with an instruction for setting or clearing a bit

Details Microprocessor with an instruction for setting or clearing a bit Microprocessor with an instruction for setting or clearing a bit

1998-01-23

2000-10-03

Eng, David Y.

Electrical computers and digital processing systems: processing

Architecture based instruction processing

G06F 930

Patent

active

061287253

ABSTRACT:
A microprocessor 1 has an instruction fetch/decode unit 10a-c, a plurality of execution units, including an arithmetic and load/store unit D1, a multiplier M1, an ALU/shifter unit S1, an arithmetic logic unit ("ALU") L1, a shared multiport register file 20a from which data are read and to which data are written, and a memory 22. Execution unit S1 has circuitry for clearing or setting a designated bit field in a source operand in one execution phase of an instruction execution pipeline.

REFERENCES:
patent: 4941085 (1990-07-01), Sakamura et al.
patent: 5210835 (1993-05-01), Sakamura et al.
patent: 5835793 (1998-11-01), Li et al.

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