Boots – shoes – and leggings
Patent
1987-03-16
1988-11-15
Harkcom, Gary V.
Boots, shoes, and leggings
371 20, 371 27, G06F 944
Patent
active
047854162
ABSTRACT:
Within a test system for testing microprocessor-based systems, an apparatus for emulating the timing characteristics of a microprocessor, including when the microprocessor goes to a "WAIT" state during the execution of an instruction cycle. A control signal RAM has a plurality of sets of instructions, each set being stored in a specific region, each set corresponding to the timing characteristics, that is the control, address and data signals, of a microprocessor. A decode RAM stores coded instructions for addressing each region of the control signal RAM. A sequence control RAM contains data for addressing each address location in the region of the control signal RAM selected by a signal input to the decode RAM. In response to the combination of a clock signal and an external ready input signal, a sequence control latch supplies address signals to the control signal RAM to access a particular instruction of the selected instruction set and supplies the same signals to the address inputs of the sequence control memory. The sequence control memory then latches the address signals for the next instruction in the sequence control latch. The control signal memory stores data for producing a "WAIT" output. A change in the external ready input signal suspends the instruction address sequencing and causes the control signal memory to produce the "WAIT" output.
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Harkcom Gary V.
Lacasse Randy W.
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