Microprocessor system with instruction pre-fetch

Details Microprocessor system with instruction pre-fetch Microprocessor system with instruction pre-fetch

1980-11-24

1983-08-30

Zache, Raulfe B.

Boots, shoes, and leggings

364200, G06F 938

Patent

active

044020422

ABSTRACT:
A single-chip microprocessor device of the MOS/LSI type contains an ALU, several interal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. Each instruction word produces a sequence of microcodes which are generated by selecting an entry point for the first address of the control ROM then executing a series of jumps, depending upon the instruction. Usually operands must be fetched from memory and the result stored in memory. Operating speed is increased by fetching the next instruction and starting to generate operand addresses before the current result has been calculated and stored. The microprocessor can perform a memory access operation and an ALU operation in the same machine cycle.

REFERENCES:
patent: 3609700 (1971-09-01), Wollum et al.
patent: 4128873 (1978-12-01), Lamiaux
Hardin, D. K., "Variable I-Fetch", IBM T.D.B., vol. 20, No. 7, Dec. 1977, pp. 2547-2548.

Affiliated with

Also associated with

Rating

Microprocessor system with instruction pre-fetch does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Microprocessor system with instruction pre-fetch, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microprocessor system with instruction pre-fetch will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-908913