Boots – shoes – and leggings
Patent
1994-12-16
1997-02-11
Bowler, Alyssa H.
Boots, shoes, and leggings
395376, 395461, 3642328, 36424341, 3642613, 364DIG1, G06F 900
Patent
active
056030452
ABSTRACT:
A Harvard architecture data processing system includes a processor, main memory, an instruction cache, and a data cache. As is generally known with the Harvard architecture, these components are interconnected by an instruction bus, an instruction address bus, a data bus, and a data address bus. The instruction cache includes a branch target section and a general instruction section. For each instruction request by the processor, both sections are examined to determine if the requested instruction is in the cache. If it is, it is transmitted from the cache to the processor. If it is not, an instruction line including the requested instruction is fetched from main memory. If the requested instruction represents a jump (the result of an unconditional branch or a conditional branch the condition of which is met) the fetched instruction line can be stored only in the branch target section. If the requested instruction is simply the one located at the address one above that of the previous instruction, the fetched instruction line can only be stored in the general instruction section. This approach preserves branch targets in cache, while allowing all cached instructions to be available to the processor irrespective of whether a jump is called for.
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Anderson Clifton L.
Bowler Alyssa H.
Odedra Dhiren R.
VLSI Technology Inc.
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