Microprocessor system for handling multiple priority levels inte

Details Microprocessor system for handling multiple priority levels inte Microprocessor system for handling multiple priority levels inte

1996-05-03

1999-02-02

An, Meng-Ai T.

395733, 395741, 395738, G06F 1300

Patent

active

058676872

ABSTRACT:
There is disclosed control circuitry for, and a method of controlling, multiple priority level interrupt request to a microprocessor in which output circuitry for outputting an interrupt identifier is operable only in response to an interrupt signal having a higher priority status than any currently executing interrupt process, and a microprocessor system and method of controlling a microprocessor system, incorporating such circuitry.

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