Boots – shoes – and leggings
Patent
1988-05-17
1989-08-22
Eng, David Y.
Boots, shoes, and leggings
364400, 364402, 364407, G06F 1300, G06F 700
Patent
active
048601985
ABSTRACT:
A microprocessor system is configured by connecting an n/2-bit memory and/or I/O to an n-bit microprocessor. The system has a read/write controller for enabling/disabling a read/write control signal for accessing the memory and/or I/O, an address latch counter for latching and updating the address, a bus converter for converting the data bus through which the data is transferred, and a timing generator. The timing generator comprises a detector for detecting that the instruction executed by the microprocessor is a word transfer instruction for the memory and/or I/O, a counter for counting the number of times a read/write control signal is generated and a timing controller for generating various timing control signals when the word transfer instruction for the memory and/or I/O is executed. When the microprocessor performs the word transfer instruction for the memory and/or I/O, the read/write control signal is enabled and disabled to perform two access cycles. The word transfer instruction can be automatically converted to two 1/2 transfer instructions.
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Eng David Y.
Kabushiki Kaisha Toshiba
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