Boots – shoes – and leggings
Patent
1991-06-03
1993-03-09
Harrell, Robert B.
Boots, shoes, and leggings
364DIG1, 3642286, G06F 1516
Patent
active
051931591
ABSTRACT:
When a coprocessor communicates a plurality of data items with a master processor and a memory according to a bus access cycle activated by the master processor, the coprocessor is supplied therein with information indicating a data storage position as a data transfer source or destination. The master processor and coprocessor independently monitor the number of the sequence of data transfers or the end of the sequence of data transfer operations. As a consequence, when executing a sequence of plural data transfer operations, the coprocessor need not receive a command from the master processor for each data transfer thereto. Further, it is not required for the coprocessor to indicate the end of the sequence of data transfer cycles to the master processor since the master processor can determine this on its own.
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Hasegawa Atsushi
Hashimoto Kouzi
Iwasaki Kazuhiko
Kawasaki Ikuya
Harrell Robert B.
Hitachi , Ltd.
Hitachi Microcomputer & Engineering, Ltd.
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