Microprocessor providing an interface between a peripheral subsy

Details Microprocessor providing an interface between a peripheral subsy Microprocessor providing an interface between a peripheral subsy

1981-02-18

1983-09-27

Gruber, Felix D.

Boots, shoes, and leggings

G06F 920

Patent

active

044070160

ABSTRACT:
A microprocessor receives addresses and data from a peripheral subsystem for use in subsequently accessing portions of the main memory of a data processing system in a controlled and protected manner. Each of the addresses is used to interrogate an associative memory to determine if the address falls within one of the subranges for a "window" on the main memory address space. If the address matches, then it is used to develop a corresponding address on the main memory address space. The data associated with the peripheral subsystem address is then passed through the interface and into the main memory at the translated memory address. Data transfer is improved by buffering blocks of data on the microprocessor. Data bytes are written into the buffer at a slower rate than data blocks are read out of the buffer and into main memory. A buffer bypass register allows single bytes of data to be transferred to a single address by bypassing the buffer. Address development and memory response signals are generated by the microprocessor rather than the peripheral subsystem processor for block transfers.

REFERENCES:
patent: 4126894 (1978-11-01), Cronshaw et al.
patent: 4145738 (1979-03-01), Inoue
patent: 4173783 (1979-11-01), Couleur et al.
patent: 4231086 (1980-10-01), Tarbox et al.
patent: 4332008 (1982-05-01), Shima et al.

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