Microprocessor PLL clock circuit with selectable delayed feedbac

Oscillators – Relaxation oscillators

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331 17, 364DIG1, 364270, 3642703, G06F 100, G06F 104, G06F 106, G06F 110

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054468671

ABSTRACT:
A circuit for use in high performance microprocessor systems which eliminates skew between a clock signal internal to the microprocessor core and inputs generated by a clock signal external to the microprocessor core. The circuit includes a phase locked loop (PLL), a delay line and a clock driver. The PLL locks and deskews the external clock edge to that of the internal clock to thereby provide an overall reduction of the setup and hold time window to satisfy the tight I/O timings required by high performance microprocessor systems. By incorporating the same PLL in all the closely coupled components of the microprocessor core, similar temperature and power supply tracking of such components is achieved. The PLL is a charge-pump based circuit of the type known in the art incorporating a phase detector, charge pump, loop filter and voltage controlled oscillator (VCO). However, the inclusion of the delay line in the feedback path of the PLL provides advantages not available from PLLs without such a delay line. A programmable tap is provided in the delay line which allows the I/O circuitry of the microprocessor to work with either CMOS or TTL input specifications. Specifically, compensation is provided for the differences in propagation delay between CMOS and TTL input buffers.

REFERENCES:
patent: 4771250 (1988-09-01), Statman et al.
patent: 5008636 (1991-04-01), Markinson et al.
patent: 5017889 (1991-05-01), Verbeek
patent: 5079519 (1992-01-01), Ashbly et al.
patent: 5218314 (1993-06-01), Efendovich et al.
patent: 5307381 (1994-04-01), Ahuja
A CMOS 100 MHz Microprocessor TA 5.1, Portland Technology Development, Intel Corporation, Joe Schutz.
Test Your Charge-Pump Phase Detectors, Electronic Design 12, Dr. William Egan, Jun. 7, 1978, pp. 134-137.
A 30-MHz Hybrid Analog/Digital Clock Recovery Circuit In 2-.mu.M CMOS, IEEE Journal of Solid-State Circuits, vol. 25, No. 6, Dec. 1990, pp. 1385-1394.

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