Microprocessor parallel additive execution of a computer count o

Details Microprocessor parallel additive execution of a computer count o Microprocessor parallel additive execution of a computer count o

1982-07-28

1984-12-04

Thomas, James D.

Boots, shoes, and leggings

G06F 738

Patent

active

044868480

ABSTRACT:
A data word of less than or equal to 2.sup.N bits is counted for the number of binary "1's" contained therein in log.sub.2 2.sup.N =N cycles of 3 steps each in a microprocessor. As a first step the data in a first register is logically ANDed in an arithmetic logic unit (ALU) with a mask constant from a first read only memory (ROM), with a first logical product result placed in a second register. As a second step the data from the first register is logically ANDed in the ALU with the same mask constant complemented, and a second logical product result is placed in the first register. Meanwhile, the first logical product result in the second register is shifted in a shift matrix in accordance with a shift count constant obtained from a second ROM. As a third step the shifted first logical product result from the shift matrix is ADDed in the ALU with the second logical product result from the first register, and a sum result is placed in the first register as data. During the N iterative cycles the mask constants of 2.sup.N bits progress (alternate 1's and 0's), (alternate pairs of 1's and 0's), . . . , (half 1's and half 0's) while the shift constants progress 2.sup.0, 2.sup.1, 2.sup.2, . . . , 2.sup.N-1. After N iterative cycles of 3 steps each, the number of binary 1's in the original data word of 2.sup.N bits is in the first register.

REFERENCES:
patent: 4189716 (1980-02-01), Krambeck
Kilburn et al., "Digital Computers at Manchester University",Proc. of the Ins. of Electrical Engineers, Oct. 1953, pp. 487-500.

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