Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1999-02-25
2001-09-18
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S210000, C712S211000, C712S245000
Reexamination Certificate
active
06292881
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to microprocessors, operation process execution methods and recording mediums, and more particularly to a microprocessor, an operation process executing means and a computer-readable recording medium capable of executing an operation process corresponding to a microcode.
Recently, the operation speed and the integration density of microprocessors have improved considerably. Such improvements have lead to improvements in the hardware technology of personal computers, portable terminal equipments and the like, and to improvements in the information processing technology of personal computers and the like.
However, due to the recent developments in the information processing technology, the operation processing system itself has become high-speed and complex. As a result, the band width of a storage part such as a cache has increased, thereby requiring the hardware and the software to be re-designed every time the band width is increased.
Accordingly, there are demands to realize a microprocessor which can be developed within a short time, without increasing the band width of the storage part such as the cache, even if the operation processing system itself becomes high-speed and complex.
2. Description of the Related Art
A description will be given of a typical conventional microprocessor which executes a predetermined operation process according to a microcode which is an instruction code.
FIG. 1
shows a hardware construction of a conventional Very Long Instruction Word (VLIW) type microprocessor.
Because of the need to execute a large amount of operation processes at a high speed, the microprocessor shown in
FIG. 1
is formed by a plurality of pipelines for carrying out a pipeline process and executing an operation process in parallel. Each pipeline is constructed from an operation instruction reading part
311
, an operation instruction decoding part
312
, a data reading part
313
, an operation process executing part
314
, and an operation result writing part
315
. Because this conventional microprocessor is formed by the plurality of pipelines, a horizontal development is made with respect to an operation process instruction which executes complex operation process instructions by the plurality of pipelines.
For example, in a case where the microprocessor is formed by four kinds of pipelines
301
,
302
,
303
and
304
as shown in
FIG. 1
, an operation result of each pipeline is written in a storage part
305
, and the operation result is read by another pipeline via the storage part
305
, so that data transfer is possible among the pipelines. In addition, if there is a conflict in the writing of the operation results from the pipelines to the storage part
305
, an arbitration process is carried out by a write arbitration part
306
to avoid the conflict.
Next, a description will be given of the functions of each of the parts forming the pipeline of the microprocessor having the above described construction.
The operation instruction reading part
311
has a function of reading (fetching) a microcode including information which indicates transfer contents of input and output data required for the operation process, and a process instruction. The process instruction refers to an instruction which is subjected to an operation processing one pipeline.
The operation instruction decoding part
312
has a function of decoding the microcode read by the operation instruction reading part
311
.
The data reading part
313
has a function of reading from the storage part
305
the input data necessary for the operation process, based on the information which indicates the transfer contents of the input and output data and is included in the microcode decoded by the operation instruction decoding part
312
.
The operation process executing part
314
has a function of carrying out a predetermined operation according to the process instruction decoded by the operation instruction decoding part
312
and the input data read by the data reading part
313
. In the conventional microprocessor, the operation process executing part
314
includes a single operation unit resource. In addition, a basic instruction which uses one operation unit resource is called a Reduced Instruction Set Computer (RISC) type instruction.
The operation result writing part
315
has a function of writing the operation result of the operation process executing part
314
in the storage part
305
.
On the other hand,
FIG. 2
is a time chart showing an operation process of a Complex Instruction Set Computer (CISC) type microprocessor.
The CISC type microprocessor is capable of processing process instructions of high-level function operation processes which are complex, such as multiplication and division, and string operation. In other words, the CISC type microprocessor can reduce the total number of instructions to be executed, by making one process instruction carry out a plurality of RISC type instructions.
A description will be given of the process of the CISC type microprocessor for an example shown in
FIG. 2
, where process instructions of an instruction “a” and an instruction “b” are to be executed. In
FIG. 2
, Fa and Fb respectively indicate times of fetch cycles of the process instructions “a” and “b”, D(
1
) through D(
4
) respectively indicate decoding times of RISC type instructions within the process instruction “a”, D(
5
) through D(
8
) respectively indicate decoding times of RISC type instructions within the process instruction “b”, R(
1
) through R(
4
) respectively indicate read times of input data necessary to execute the process instruction “a”, R(
5
) through R(
8
) respectively indicate read times of input data necessary to execute the process instruction “b”, E(
1
) through E(
4
) respectively indicate execution times of the RISC type instructions within the process instruction “a”, E(
5
) through E(
8
) respectively indicate execution times of the RISC type instructions within the process instruction “b”, W(
1
) through W(
4
) respectively indicate write times of operation results of the RISC type instructions within the process instruction “a”, and W(
5
) through W(
8
) respectively indicate write times of operation results of the RISC type instructions within the process instruction “b”. In addition, it is assumed for the sake of convenience that each of the process instructions “a” and “b” is made up of four RISC type instructions, for example.
The CISC type microprocessor fetches the process instruction “a” in 4 cycles (Fa), and carries out a decoding process (D(
1
) through D(
4
)), a read process (R(
1
) through R(
4
)), an instruction execution process (E(
1
) through E(
4
)), and a write process (W(
1
) through W(
4
)) in the sequence shown, for every RISC type instruction within the process instruction “a”. Hence, the processing of the process instruction “a” ends in 11 cycles as shown in FIG.
2
.
In addition, simultaneously as the decoding process (D(
1
) through D(
4
)) after fetching the process instruction “a”, the CISC type microprocessor fetches the next process instruction “b” (Fb), and carries out a decoding process (D(
5
) through D(
8
)), a read process (R(
5
) through R(
8
)), an instruction execution process (E(
5
) through E(
8
)), and a write process (W(
5
) through W(
8
)) in the sequence shown, for every RISC type instruction within the process instruction “b”. Therefore, the processing of the process instruction “a” and he process instruction “b” ends in a total of 15 cycles, as shown in FIG.
2
.
According to the CISC type microprocessor, a cycle per instruction (CPI) becomes long by making one process instruction carry out a plurality of RISC type instructions, but the number of instructions executed within the entire program can be reduced.
On the other hand,
FIG. 3
is a time chart showing an operation process of a RISC type microprocessor.
The RISC type microprocessor is designed to compensate for the low-level function of the hardware using software t
Iwasaki Nobuyuki
Nomura Yuji
Tanaka Ritsuko
Tsuruta Toru
Fujitsu Limited
Pan Daniel H.
Staas & Halsey , LLP
LandOfFree
Microprocessor, operation process execution method and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Microprocessor, operation process execution method and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microprocessor, operation process execution method and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2443926