Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Patent
1999-05-25
2000-10-31
An, Meng-Ai T.
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
708401, 708403, 708404, 708405, 708406, 712 3, 712 4, 712 5, 712 6, G06F 1714
Patent
active
061416738
ABSTRACT:
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local central processing unit (CPU) bus to a conventional processor. The MEU employs vector registers, a vector arithmetic logic unit (ALU), and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.
REFERENCES:
patent: 3541516 (1970-11-01), Senzig
patent: 3701977 (1972-10-01), Mendelson et al.
patent: 4707800 (1987-11-01), Montrone et al.
patent: 4725973 (1988-02-01), Matsuura et al.
patent: 4782441 (1988-11-01), Inagami et al.
patent: 4783736 (1988-11-01), Ziegler et al.
patent: 4849882 (1989-07-01), Aoyama et al.
patent: 4884197 (1989-11-01), Sachs et al.
patent: 4891754 (1990-01-01), Boreland
patent: 5025407 (1991-06-01), Gulley et al.
patent: 5073864 (1991-12-01), Methvin et al.
patent: 5181183 (1993-01-01), Miyazaki
patent: 5187796 (1993-02-01), Wang et al.
patent: 5193167 (1993-03-01), Sites et al.
patent: 5226171 (1993-07-01), Hall et al.
patent: 5235536 (1993-08-01), Matsubishi et al.
patent: 5251323 (1993-10-01), Isobe
patent: 5307300 (1994-04-01), Komoto et al.
patent: 5335330 (1994-08-01), Inoue
patent: 5434592 (1995-07-01), Dinwiddle, Jr. et al.
patent: 5437043 (1995-07-01), Fujii et al.
patent: 5453945 (1995-09-01), Tucker et al.
patent: 5471637 (1995-11-01), Pawlowski et al.
patent: 5481713 (1996-01-01), Westmore et al.
patent: 5511219 (1996-04-01), Shimony et al.
patent: 5513366 (1996-04-01), Agarwal et al.
patent: 5537640 (1996-07-01), Pawlowski et al.
patent: 5627981 (1997-05-01), Adler et al.
patent: 5640588 (1997-06-01), Vegesna et al.
patent: 5644520 (1997-07-01), Pan et al.
patent: 5655096 (1997-08-01), Branigin
patent: 5669013 (1997-09-01), Watamabe et al.
patent: 5673408 (1997-09-01), Shebanow et al.
patent: 5673426 (1997-09-01), Shen et al.
patent: 5692211 (1997-11-01), Gulick et al.
patent: 5745721 (1998-04-01), Beard et al.
patent: 5801975 (1998-09-01), Thayer et al.
patent: 5845083 (1998-12-01), Hamadani et al.
patent: 5850227 (1998-12-01), Longhenry et al.
patent: 5893145 (1999-04-01), Thayer et al.
patent: 5909572 (1999-06-01), Thayer et al.
Vasudev Bhaskaran and Konstantinos Konstantinides, "Image Compression Standard and Architectures", Class Notes ACM Multimedia 94, San Francisco, CA, Oct. 1994, 58 pages.
Kohn, L., et al., "The Visual Instruction Set (VSI) in UltraSPARC," SPARC Technology Business--Sun Microsystems, Inc., 1996 IEEE, pp. 462-489.
Gwennap, Linley, "UltraSPARC Adds Multimedia Instructions--Other New Instructions Handle Unaligned and Little-Endian Data," Microprocessor Report, Dec. 5, 1994, 99. 16-18.
Lee, Ruby, B., "Realtime MPEG Video via Software Decompression on a PA-RISC Processor," Hewlett-Packard Company, 1995 IEEE, pp. 186-192.
Mattison, Phillip E., "Practical Digital Video With Programming Examples in C," Wiley Professional Computing, pp. 158-178.
Zhou, Chang-Guo, et al., "MPEG Video Decoding With The UltraSPARC Visual Instruction Set," Sun Microsystems, Inc., 1995 IEEE, pp.470-474.
Mahlke, et al., "A Comparison of Full and Partial Predicated Execution Support of ILP Processor," 1995, IEEE Publication, pp. 138-149.
Favor John Gregory
Thayer John S.
Weber Frederick D.
Advanced Micro Devices , Inc.
An Meng-Ai T.
Compaq Computer Corp.
Daffer Kevin L.
Kowert Robert C.
LandOfFree
Microprocessor modified to perform inverse discrete cosine trans does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Microprocessor modified to perform inverse discrete cosine trans, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microprocessor modified to perform inverse discrete cosine trans will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2064869