Boots – shoes – and leggings
Patent
1984-12-13
1986-09-30
Thomas, James D.
Boots, shoes, and leggings
G06F 1300
Patent
active
046150048
ABSTRACT:
A microprocessor having a single common data bus (17) to which the output (33) of the arithmetic-logic unit (11) as well as input and output of the data memory (13) are connected without intermediate buffer registers. Of the working registers (21, 23, 25, 27) connected to the ALU inputs, one group (21, 23) is loaded from the common data bus and the other group (25, 27), used as accumulators, is directly loaded from the ALU output. Specific control circuitry (51, 53, 55, 57, 59, 61) allows selective storing of ALU output values into accumulators (25, 27), and simultaneous transfer with selective scaling into another register and into an addressed memory location within the same cycle during which the instruction was executed.
REFERENCES:
patent: 4048481 (1977-09-01), Bailey, Jr. et al.
patent: 4086626 (1978-04-01), Chung
patent: 4106090 (1978-08-01), Erickson et al.
Chevillat Pierre R.
Kaeser Hans P.
Maiwald Dietrich G. U.
Ungerboeck Gottfried
Brodie R. Bruce
Clark David L.
International Business Machines - Corporation
Thomas James D.
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