Microprocessor including device for detecting predetermined inst

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395500, 3951831, 364264, 3642641, 3642645, 364DIG1, G06F 1130

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054407001

ABSTRACT:
A microprocessor comprises a program counter for holding the address where the halt instruction is detected, a terminal for outputting a special status signal, a bus cycle control unit for generating the halt instruction indication bus cycle, and an execution unit for transferring the content of the program counter to the bus cycle control unit and requesting the start of the halt instruction indication bus cycle.
Thus, the address where the processor halt instruction has been executed and other internal information are informed to an external, so that precise and certain debugging environment is obtained.

REFERENCES:
patent: 4308581 (1981-12-01), Raghunathan
patent: 4881228 (1989-11-01), Shouda
patent: 5134701 (1992-07-01), Mueller et al.
patent: 5142679 (1992-08-01), Owaki et al.
patent: 5289587 (1994-02-01), Razban
patent: 5361348 (1994-11-01), Nakamoto
"80386 Hardware Reference Manual";1986, Intel Corporation, US, Santa Clara; pp. 3-18, line 1--pp. 3-19, line 11.

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