Microprocessor having timer circuit generating complementary non

Details Microprocessor having timer circuit generating complementary non Microprocessor having timer circuit generating complementary non

1996-03-13

1999-08-03

Gordon, Paul P.

Boots, shoes, and leggings

364136, 364141, 364486, 364487, G05B 1101

Patent

active

059333448

ABSTRACT:
Two up-counters and two down-counters having a time difference corresponding to a dead time are provided to realize an up-down symmetric count, such that the up-counters and the down-counters are made to count the lower limit and the upper limit (a 1/2 period+the dead time), the up-counter for counting a relatively large value and the down-counter for counting a relatively large value are made to contact at the upper limit, the up-counter for counting a relatively small value and the down-counter for counting a relatively small value are made to intersect at a count value corresponding to the 1/2 period, the up-counter for counting the relatively large value and the down-counter for counting the relatively large value are made to intersect at the count value corresponding to the dead time, and the up-counter for counting the relatively small value and the down-counter for counting the relatively small value are made to contact at the lower limit.

REFERENCES:
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patent: 5095878 (1992-03-01), Kumagai et al.
patent: 5132682 (1992-07-01), Higgins et al.
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patent: 5476010 (1995-12-01), Fleming et al.
patent: 5479532 (1995-12-01), Abel et al.
patent: 5592403 (1997-01-01), Trager et al.
patent: 5614720 (1997-03-01), Morgan et al.
Excerpts from "H8/3003 Hardware Manual" issued by Hitachi in Mar., 1993.

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