Patent
1995-09-07
1998-12-08
Auve, Glenn A.
39580038, G06F 1300
Patent
active
058482474
ABSTRACT:
A microprocessor comprising a bus state controller and for use in a personal computer or the like. The bus state controller includes control registers such as wait controllers, and in parallel controls the interfaces of various semiconductor memories (ROM, burst ROM, SRAM, PSRAM, DRAM and synchronous RAM) and PC cards (memory and I/O cards). Also included in the bus state controller is a control register for controlling the time to set up PC card start signals where a synchronous DRAM(s) is configured. The address space of an external bus of the microprocessor is divided into a predetermined number of areas to which the semiconductor memories and PC cards are fixedly assigned. The microprocessor further comprises a memory management unit for converting an internally prepared logical address to a physical address.
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"RISC Chip SH7064 Directly Connectable to Synchronous DRAM" by Nikkei Electronics published by Nikkei-MacGraw-Hill, Inc. (Feb. 14, 1994, pp. 79-91).
Kawasaki Ikuya
Matsui Shigezumi
Narita Susumu
Nemoto Masato
Auve Glenn A.
Hitachi , Ltd.
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