Microprocessor having instruction fetch and execution overlap

Details Microprocessor having instruction fetch and execution overlap Microprocessor having instruction fetch and execution overlap

1978-09-25

1981-03-10

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 938

Patent

active

042557852

ABSTRACT:
A microprocessor having separate bidirectional instruction and data busses is disclosed which allows the fetching of instructions from a program memory to be overlapped with the execution of instructions previously fetched. Program instructions are stored in an internal read-only-memory and/or in an external read-only-memory. Variable data is stored in an internal register array. During a given machine cycle, a data word in the register array can be transferred to an arithmetic-logic unit by a bidirectional data bus. The result of the operation performed by the arithmetic-logic unit can be transferred by the data bus back to the register array and stored in the selected location during the same machine cycle. Simultaneously, the contents of a program counter are transferred by a bidirectional instruction memory bus to the program memory to access the instruction to be executed on the following machine cycle. The addressed instruction is transferred from the program memory by the bidirectional instruction memory bus to the microprocessor and is stored to be decoded and executed on the following machine cycle.

REFERENCES:
patent: 3462742 (1969-08-01), Miller et al.
patent: 3766527 (1973-10-01), Briley
patent: 3811114 (1974-05-01), Lemay et al.
patent: 3886523 (1975-05-01), Ferguson et al.
patent: 3956738 (1976-05-01), Tessera
patent: 4040031 (1977-08-01), Cassonnet
patent: 4050058 (1977-09-01), Garlic
patent: 4079455 (1978-03-01), Ozga
patent: 4110822 (1978-08-01), Porter et al.
An Introduction to Microcomputers, vol. II, Some Real Products, authored and published by Adam Osborne and Associates, Inc., 1977, pp. 6-18, 6-19.

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