Microprocessor having index register coupled to serial-coupled a

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G06F 920

Patent

active

040328961

ABSTRACT:
A method of generating addresses in a microprocessor includes steps of storing first informationrepresentative of a first address in a first register, such as a program counter register. The first information is transmitted to a first address bus in order to effect addressing the contents of a first location represented by the first address. The first information is also transmitted via the address bus to an incrementor-decrementor circuit. The first information is incremented to produce second information representative of the address of the next instruction during the addressing of the first location. The second information is then transmitted to the first register.

REFERENCES:
patent: 3391394 (1968-07-01), Ottaway et al.
patent: 3702988 (1972-11-01), Haney et al.
patent: 3757306 (1973-09-01), Boone
patent: 3938098 (1976-02-01), Garlic
patent: 3943495 (1976-03-01), Garlic

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