Microprocessor having improved functional redundancy monitor mod

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371 12, G06F 1516, G06F 702

Patent

active

051827549

ABSTRACT:
A plurality of gates are arranged between a coincidence circuit and a group of comparators which compare data outputted by a processor's output buffers, and data inputted to the processor via terminals during a monitor mode. An invalid byte information generator is connected to the gates and applies a signal selected to mask the effects of write instructions being executed on an incomplete word and therefore prevents the generation of an erroneous mismatch signal.

REFERENCES:
patent: 3810119 (1974-05-01), Zieve et al.
patent: 4012717 (1977-03-01), Censier et al.
patent: 4049957 (1977-09-01), Kera et al.
patent: 4400792 (1983-08-01), Strelow
patent: 4839908 (1989-01-01), Takayama

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