Patent
1993-10-18
1998-08-11
Treat, William M.
395571, 395572, 39580023, G06F 926
Patent
active
057940266
ABSTRACT:
A processor architecture and methodology for executing a condition dependent instruction over a plurality of execution stages in a microprocessor. The microprocessor includes a memory for storing microinstructions. The method involves various steps. In one step, an instruction is received. In another step, a first microinstruction is issued from the memory. This first microinstruction comprises a control and a base address. In yet another step, a secondary address is determined, external from the memory, by evaluating a plurality of predetermined data. In a still another step, the base address and the secondary address are combined to form a destination address in response to the control signal, wherein the destination address identifies a second microinstruction in the memory to execute a successive stage for the received instruction.
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Hervin Mark W.
McMahon Ronald S.
Maxin John L.
National Semiconductor
Treat William M.
Viger Andrew S.
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