Boots – shoes – and leggings
Patent
1989-06-26
1991-10-15
Lee, Thomas C.
Boots, shoes, and leggings
364265, 3642661, 3642662, 3642666, G06F 1100
Patent
active
050579991
ABSTRACT:
A microprocessor including a CPU, an instruction memory (ROM) with a sequencer in the CPU that sends out a fetch signal for an instruction, and an address decoder that decodes the fetch signal and sends a signal to the ROM allowing the fetch signal to fetch an instruction if the address is correct.
REFERENCES:
patent: 4317171 (1982-02-01), Maejima et al.
patent: 4402044 (1983-08-01), McDonough et al.
patent: 4441154 (1984-04-01), McDonough et al.
patent: 4534018 (1985-08-01), Eckert et al.
patent: 4534030 (1985-08-01), Pacz et al.
patent: 4590552 (1986-05-01), Guttag et al.
patent: 4667087 (1987-05-01), Quintana
patent: 4685056 (1987-08-01), Barnsdale, Jr. et al.
patent: 4727549 (1988-02-01), Tulpule et al.
patent: 4763296 (1988-08-01), Gercekci
patent: 4791557 (1988-12-01), Angel et al.
patent: 4874935 (1989-10-01), Younger
Kase Kiyoshi
Suzuki Minoru
Lee Thomas C.
Lewis Charles R.
Nippon Motorola Ltd.
Powell Jordan C.
Treat William M.
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