Microprocessor having a power-saving fetch and decoding unit...

Details Microprocessor having a power-saving fetch and decoding unit... Microprocessor having a power-saving fetch and decoding unit...

2007-10-30

2007-10-30

Kim, Hong (Department: 2185)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate variable length...

C712S211000, C712S024000, C713S320000

Reexamination Certificate

active

11036740

ABSTRACT:
A microprocessor having a power-saving fetch and decoding unit for fetching and decoding compressed program instructions and having a program instruction sequencer is disclosed. The microprocessor based on the inventive architecture has a power-saving fetch and decoding unit for fetching and decoding program instructions. The fetch and decoding unit has a program instruction memory which receives a sequential program instruction address addressing the next program instruction memory line which is to be read, having at least one program instruction memory line which can store an indicator flag, a long program instruction index, a short program instruction and a first source register address. A directory memory receives the long program instruction index (6) addressing the next directory memory line which is to be read. A short program instruction decoding unit for decoding the short program instruction which has been read from the program instruction memory and for providing a first program instruction counter.

REFERENCES:
patent: 6209079 (2001-03-01), Otani et al.
patent: 2002/0069345 (2002-06-01), Mohamed et al.
patent: 2003/0061473 (2003-03-01), Revilla et al.

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