Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1999-01-11
2002-08-13
Niebling, John F. (Department: 2812)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S209000
Reexamination Certificate
active
06434690
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a logic semiconductor integrated circuit (LSI) provided with a central processing unit (CPU) and a digital signal processing unit (DSP) and formed into a semiconductor integrated circuit and an art effectively applied to a data processor (e.g. single-chip microprocessor or single-chip microcomputer) for high-speed processing.
Japanese Patent Application No. 296778/1992 (corresponding to U.S. Pat. No. 08/145157, now abandoned) is a document describing a single-chip microcomputer in which an arithmetic and logic unit and a multiplier are mounted on the same semiconductor chip.
According to the above Invention, a logic LSI chip includes a central processing unit, a bus, a memory, and a multiplier and particularly has a command signal line for transferring a command for a multiplication instruction related to read data from the central processing unit to the multiplier while reading the data out of the memory. As a result, because the command of the multiplication instruction related to read data is transferred from the central processing unit to the multiplier while the central processing unit reads data out of the memory, it is possible to directly transfer data between the memory and the multiplier.
SUMMARY OF THE INVENTION
The present inventor and others studied formation of a central processing unit and a digital signal processing unit (DSP) in a semiconductor integrated circuit (LSI) and acceleration of digital signal processing.
The above document realizes acceleration of multiplication by making it possible to directly transfer data from a memory to a multiplier. However, when assuming pipeline processing of instruction execution by a central processing unit, the above document does not consider the situation in which the fetch cycle of an instruction to be executed by a central processing unit competes with the memory access cycle for multiplication.
Moreover, the above document does not consider reading a plurality of operands for addition and multiplication out of a memory in parallel and accelerating operational processing. Furthermore, in this case, it is found by the present inventor and others that the operational easiness of a microcomputer is deteriorated unless considering the relation with external access by the central processing unit.
Furthermore, it is found by the present inventor and others that devising the assignment of codes to a CPU instruction (first instruction) and a DSP instruction (second instruction) and the format so the DSP instruction are also necessary to restrain the increase of the logic scale of an instruction decode circuit to the utmost.
It is an object of the present invention to accelerate digital signal processing by mounting a central processing unit and a digital signal processing unit on one semiconductor integrated circuit.
It is another object of the present invention to restrain the increase of the physical scale of a semiconductor integrated circuit when mounting a central processing unit and a digital signal processing unit on the semiconductor integrated circuit.
It is still another object of the present invention to provide a data processor whose operational easiness is improved and which includes a central processing unit and a digital processing unit on the same semiconductor chip.
It is still another object of the present invention to provide a data processor in which digital signal processing is accelerated.
It is still another object of the present invention to provide an instruction format (instruction set) preferably applied to a data processor including a central processing unit and a digital signal processing unit in the same semiconductor chip.
It is still another object of the present invention to provide an instruction format (instruction set) capable of restraining the increase of the logic scale of an instruction decode circuit in a data processor including a central processing unit and a digital signal processing unit in the same semiconductor chip.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
A typical embodiment of the invention disclosed in this application is briefly described below.
That is, a semiconductor integrated circuit (microcomputer) comprises a semiconductor chip including:
a central processing unit (
2
);
first to third address buses (IAB, YAB, and XAB) to which an address is selectively transferred from the central processing unit;
first memories (
5
and
7
) connected to the first address bus (IAB) and the second address bus (YAB) and to be accessed by an address sent from the central processing unit;
second memories (
4
and
6
) connected to the first address bus (IAB) and the third address bus (XAB) and to be accessed by an address sent from the central processing unit;
a first data bus (IDB) for transferring data, which is connected to the first and second memories and the central processing unit;
a second data bus (YDB) for transferring data, which is connected to the first memories;
a third data bus (XDB) for transferring data, which is connected to the second memories;
an external interface circuit (
12
) connected to the first address bus and the first data bus;
a digital signal processing unit (
3
) connected to the first to third data buses and synchronously operated by the central processing unit; and
a control signal line for transferring a DSP control signal (
20
) for controlling the operation of the digital signal processing unit from the central processing unit to the digital signal processing unit.
According to the above means, a built-in or an internal memory is divided into the following two types by considering multiply and accumulate operation: first memories (
5
and
7
) and second memories (
4
and
6
). Then, the central processing unit (
2
) is made possible to access the first and second memories by the third internal buses (XAB and XDB) and the second internal buses (YAB and YDB) in parallel. Thereby, it is possible to transfer two data values to the digital signal processing unit from the built-in memory at the same time.
Moreover, because the third internal buses (XAB and XDB) and the second internal buses (YAB and YDB) are also separated from the first internal buses (IAB and IDB) to be interfaced with an external unit, the central processing unit can access an external memory in parallel with the access to the second memories (
4
and
6
) and the first memories (
5
and
7
) by using the first internal buses (IAB and IDB).
Thus, because the data processor of the present invention has three internal address buses (IAB, XAB, and YAB) and three internal data buses (IDB, XDB, and YDB) and the first and third internal buses are connected to the central processing unit (
2
), the processor can access different memories at the same clock cycle by using the first to third internal buses. Therefore, even if a program or data is present in an external memory, the data processor of the present invention can easily accelerate arithmetic processing.
To improve the operational easiness of a microcomputer, the first and second memories are preferably RAM and ROM, respectively.
To accelerate generation of addresses for repetition of the multiply and accumulate operation in the central processing unit, it is preferable to provide a modulo address output portion (
200
) for the central processing unit. In this case, it is preferable that an address generated by the modulo address output portion can selectively be output to the second or third address bus.
The digital signal processing unit includes first to third data buffer means (MDBI, MDBY, and MDBX) to be individually interfaced with the first to third data buses (IDB, YDB, and XDB), a plurality of register means (
305
to
308
) being made connectable to each data buffer means through an internal bus, a multiplier (
304
) and an arithmetic and logic operation unit (
302
) connected to the internal bus, and a decoder (
34
) for decoding the DSP
Akao Yasushi
Baba Shiro
Baji Toru
Hasegawa Hironobu
Kiuchi Atsushi
Hitachi , Ltd.
Loudermilk & Associates
Niebling John F.
Whitmore Stacy
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