Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1999-01-07
2001-06-26
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S210000
Reexamination Certificate
active
06253305
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a microprocessor that processes data according to directions in a program, specifically to a microprocessor for supporting reduction of program codes in size.
(2) Description of the Prior Art
In these days, high-performances are expected for new microprocessor-embedded products. In order to realize such high-performance products, the programs of the microprocessors grow larger and larger. However, in the microprocessor-embedded products, the program should be stored in one or more ROMs. As a result, if the codes used in the programs increase in size, the capacity of a ROM and/or the number of ROMs should also increase, which is an obstacle in developing low-cost products. Therefore, it is desired to compress the code size as much as possible when such products are developed.
<First Conventional Technique>
One conventional technique for compressing the code size compresses the code size of each instruction executed by the microprocessor (e.g. NEC's V800 series and Hitachi's SH7000 series). The microprocessors of this technique execute instructions whose size is smaller than that of a data bus, Arithmetic Logic Unit (ALU), or registers (hereinafter ALU size). For example, the microprocessors execute 16-bit instructions while the ALU size is 32 bits.
The technique enables the replacement of a 32-bit instruction by a 16-bit instruction, thereby excluding unnecessary bits and efficiently compressing the total code size for a program.
However, this First Conventional Technique has a problem as described below.
Although the instruction size is smaller than the ALU size, the instruction size should be equal to or n times as large as the size of the instruction decoder of the microprocessor (n is integer). That is, an instruction is extended in units of 8 bits. For example, if the decoder is 8 bits in size, the instruction size should be any of 8, 16, 24, 32, . . . bits. The unit for the extension cannot be reduced to below 8 bits. As a result, even if 8 bits are not required for representing a value, 8 bits must be used. This creates a waste in the size of program codes due to the requried use of unnecessary bits.
FIG. 1
shows a format of an instruction used in a conventional microprocessor. The instruction, “add #4,d0,” instructs the microprocessor to add immediate value “4” to a value stored in register d
0
. The instruction uses 16 bits in total including 8 bits for specifying operation code “add #n,d0” and 8 bits for the immediate value “#n” which is “4” in this case. However, 8 bits are more than required to represent the value “4.” An integer ranging from “−8” to “+7” requires only 4 bits. That means, 16 bits are used for the instruction which requires only 12 bits. This creates a waste in the size of program code due to the use of unnecessary bit.
<Second Conventional Technique>
A Second Conventional Technique for compressing the code size is a method for effectively reading/writing data from/into a memory. This is achieved, e.g., by improving an addressing mode used in a data transfer instruction.
Both of
FIGS. 2A and 2B
are programs by which data is read/written from/onto a memory. Both instruct the microprocessor to read a value stored in a memory, compute with the value, and store the computation result in the memory.
Instruction a
1
in
FIG. 2A
is a load instruction by which a value stored in a location in a memory specified by an absolute address is read into register D
0
. Instruction a
2
is an add instruction by which a value stored in register D
1
is added to a value in register D
0
, then the result value is stored in register D
0
. Instruction a
3
is a store instruction by which a value stored in register D
0
is stored in a location in a memory specified by an absolute address. The basic part of these instructions has a length of 8 bits. An absolute address has a length of 16 bits. Accordingly, the total code size of the
FIG. 2A
program is 7 bytes. That means, 7 bytes are used for a set of data reading and writing from/into the memory.
In the
FIG. 2A
program, a 16-bit absolute address is used for each of two memory accesses. In the
FIG. 2B
program, an address register is used for memory accesses.
The program in
FIG. 2B
differs from that in
FIG. 2A
in that first it transfers an absolute address of the memory to an address register (instruction b
1
), secondly it transfers data from the memory to register D
0
by specifying the address register (instruction b
2
), and thirdly it stores the computation result in the memory by specifying the address register (instruction b
4
).
Although the
FIG. 2B
program additionally includes an instruction for transferring an absolute address to an address register, only instruction b
2
includes an absolute address. As a result, the total code size is reduced by one byte compared with the
FIG. 2A
program.
A large amount of program space can be reduced in a microprocessor if the code size for a set of memory accesses is reduced.
However, a problem of the Second Conventional Technique is that address registers are occupied when they are used for specifying absolute addresses of a memory. Therefore, a processor having fewer address registers may not always be able to use this method. Also, since a microprocessor, specifically a built-in microprocessor, frequently reads/writes data from/into a memory, address registers may not be used for other operations.
SUMMARY OF THE INVENTION
It is therefore a first object of the present invention to provide a microprocessor which executes instructions reduced effectively by liberating the instructions from a limitation that the instruction size should be equal to or n times as large as the size of the instruction decoder of the microprocessor (n is integer), thereby enabling the production of a program having codes with less size than conventional programs with the same contents.
It is a second object of this invention to provide a microprocessor which enables the reduction of the code size without occupying address registers.
The first object is fulfilled by a microprocessor for supporting reduction of codes in size, comprising: a decoder for decoding instructions which are “w” in length represented by expression w=a+nb, wherein “a” represents a maximum length of code at each decoding by the decoder, “n” an integer of 0 or larger, and “b” a positive integer smaller than “a,” wherein an instruction is divided into one or more codes, and wherein the instructions include at least an instruction which is “a” in length and an instruction which is “(a+b)” in length; and an executing means for processing data based on information obtained from the instructions decoded by the decoding means.
This microprocessor extends instructions without a limitation that the instruction size should be equal to or n times as large as the size of the instruction decoder of the microprocessor (n is integer). That is, the microprocessor extends instructions in units of “b” which is smaller than “a.” As a result, the present invention decreases unnecessary bits included in codes for instructions, reducing a total program size.
In the above microprocessor, “a” may equal to a word in length, and “b” may equal to a half word in length, wherein the word and the half word are units of length.
This microprocessor extends instructions in units of half words. Then, instruction length “w” will be any of a, 1.5a, 2a, 2.5a, 3a, . . . . When this happens, the amount of information specified by an instruction increases with less bits. For example, instructions can be defined with more information and data can be specified with more information.
The microprocessor may further comprise: an instruction buffer for holding a prefetched instruction; a storage means for storing information of a state of the instruction held in the instruction buffer for each half word; a first judging means for judging whether a code to be decoded next is a half word or a word in length based on
Deguchi Masashi
Hamaguchi Toshifumi
Matsumoto Masahiko
Matsuzaki Toshimichi
Tanase Yutaka
Coleman Eric
Matsushita Electric - Industrial Co., Ltd.
Price and Gess
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