Microprocessor for executing byte compiled JAVA code

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C712S229000

Reexamination Certificate

active

07917732

ABSTRACT:
A microprocessor architecture for executing byte compiled Java programs directly in hardware. The microprocessor targets the lower end of the embedded systems domain and features two orthogonal programming models, a Java model and a RISC model. The entities share a common data path and operate independently, although not in parallel. The microprocessor includes a combined register file in which the Java module sees the elements in the register file as a circular operand stack and the RISC module sees the elements as a conventional register file. The integrated microprocessor architecture facilitates access to hardware-near instructions and provides powerful interrupt and instruction trapping capabilities.

REFERENCES:
patent: 5696959 (1997-12-01), Guttag et al.
patent: 5812868 (1998-09-01), Moyer et al.
patent: 5937193 (1999-08-01), Evoy
patent: 5978901 (1999-11-01), Luedtke
patent: 6021469 (2000-02-01), Tremblay et al.
patent: 6026485 (2000-02-01), O'Connor et al.
patent: 6076155 (2000-06-01), Blomgren et al.
patent: 6324686 (2001-11-01), Komatsu et al.
patent: 6332215 (2001-12-01), Patel et al.
patent: 6338160 (2002-01-01), Patel et al.
patent: 6654954 (2003-11-01), Hicks
patent: 6826749 (2004-11-01), Patel et al.
patent: 6990567 (2006-01-01), Cohen et al.
patent: 2004/0015678 (2004-01-01), Strom
patent: WO-97/22924 (1997-06-01), None
patent: WO-97/27537 (1997-07-01), None
patent: WO-00/34844 (2000-06-01), None
patent: WO-02/086699 (2002-10-01), None
O. Strom et al., “A Novel Microprocessor Architecture for Executing Byte Compiled Java Code”, Proceedings of the World Computer Congress, Aug. 2000, 7 pages.
O. Strom et al., “A Study of Dynamic Instruction Frequencies in Byte Compiled Java Programs,” Proceedings of Euromicro, Sep. 1999, 4 pages.
O. Strom, “VLSI Realization of an Embedded Microprocessor Core with Support for Java Instructions,” Ph.D. thesis, Norwegian University of Science and Technology, Nov. 2000, 160 pages.
“ARM® Architecture Extensions for Java Applications”,Jazelle website, 6 pgs.
“International Application Serial No. PCT/US02/10389, International Preliminary Examination Report dated Aug. 19, 2003”, 9 pgs.
“International Application Serial No. PCT/US02/10389, International Search Report mailed Feb. 17, 2003”, 5 pgs.
“Jazelle™ Technology for Java Applications”,Jazelle website, ARM Product Information, 4 pgs.
“Republic of Korean Application Serial No. 10-2003-7013746, Office Action mailed Apr. 28, 2008”, 8 pgs.
Betts, A. K, et al., “SMILE: A Scalable Microcontroller Library Elements”,Microprocessing and Microprogramming, vol. 39(Issue 2-5), (1993), 259-262.
Clarke, P., “ARM Tweaks CPU Schemes to Run Java”,Electronic Engineering Times, CMP Media, Inc., © Oct. 2000, 2 pgs.
Strom, O., et al., “A Novel Approach for Executing Byte Compiled Java Code in Hardware”,ICCA Newsletter, (Jun. 2000).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Microprocessor for executing byte compiled JAVA code does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Microprocessor for executing byte compiled JAVA code, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microprocessor for executing byte compiled JAVA code will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2623396

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.