Electrical computers and digital processing systems: processing – Architecture based instruction processing – Multiprocessor instruction
Patent
1996-04-02
1999-10-19
An, Meng-Ai T.
Electrical computers and digital processing systems: processing
Architecture based instruction processing
Multiprocessor instruction
712214, 712212, G06F 938
Patent
active
059681624
ABSTRACT:
A microprocessor is provided which detects an escape instruction. The escape instruction indicates that subsequent instructions belong to an alternate instruction set. In one embodiment, the number of subsequent instructions which belong to the alternate instruction set is encoded in the escape instruction. The subsequent instructions are routed to an execution unit or a separate processor for execution. Each instruction sequence within a program may be coded using the instruction set which most efficiently executes the function corresponding to the instruction sequence. In one embodiment, the microprocessor executes the x86 instruction set and the alternate instruction set is the ADSP 2171 instruction set. The escape instruction is defined using a previously undefined opcode within the x86 instruction set. Complex mathematical functions (which are more efficiently executed within a DSP) may be performed more efficiently than previously achievable using the x86 instruction set alone. Portions of the program which may be executed more efficiently using x86 instructions may be coded in the x86 instruction set, while portions of the program which may be executed more efficiently using DSP instructions may be coded in the DSP instruction set.
REFERENCES:
patent: 4095266 (1978-06-01), Carubia et al.
patent: 4554627 (1985-11-01), Holland et al.
patent: 4763294 (1988-08-01), Fong
patent: 4870614 (1989-09-01), Quatse
patent: 5481743 (1996-01-01), Baxter
J. C. Desaultels, "New Instruction and Extended Instruction Handling," IBM Technical Disclosure Bulletin, vol. 21, No. 1, Jun. 1978, New York US, pp. 201-202.
International Search Report for PCT/US 96/19587 dated Apr. 28, 1997.
Advanced Micro Devices , Inc.
An Meng-Ai T.
Kivlin B. Noel
Patel Gautam R.
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