Microprocessor configured to execute a prefetch instruction incl

Details Microprocessor configured to execute a prefetch instruction incl Microprocessor configured to execute a prefetch instruction incl

1998-01-12

1999-08-31

Maung, Zarni

Electrical computers and digital processing systems: processing

Instruction fetching

Prefetching

G06F 900

Patent

active

059448156

ABSTRACT:
A microprocessor is configured to execute a prefetch instruction including an access count field defining an access count corresponding to a cache line identified by the prefetch instruction. The access count indicates a number of accesses expected to the cache line. The microprocessor attempts to retain the cache line until at least the number of accesses specified by the access count are recorded. Effectively, a "lifetime" for the cache line to be stored in the cache is specified. The lifetime indicates not only how long the cache line should be retained in the cache (in terms of the number of cache accesses), but also more accurately indicates the time at which the cache line can be removed from the cache (i.e. upon expiration of the access count). In one embodiment, a prefetched cache line and the corresponding access count are stored in a data cache within the microprocessor. The stored access count is decremented upon access to the cache line. The data cache attempts to allocate storage for a cache miss in a manner which does not displace the prefetched cache line at least until the corresponding access count expires. The present embodiment may additionally include a victim cache for storing prefetched cache lines which are selected by the data cache for replacement prior to expiration of the corresponding access count.

REFERENCES:
patent: 5761468 (1998-06-01), Emberson
patent: 5813041 (1998-09-01), McIntyre, Jr. et al.
patent: 5875482 (1999-02-01), McIntyre, Jr. et al.
"PowerPC: Microprocessor Developer's Guide", Sams Publishing, Indianapolis, Indiana, 1995, pp. 212-213.

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