Communications: electrical – Digital comparator systems
Patent
1974-10-30
1977-01-18
Nusbaum, Mark E.
Communications: electrical
Digital comparator systems
G06F 900
Patent
active
040042812
ABSTRACT:
A program register is coupled between a data bus N bits wide and an address bus N bits wide for storing the address of the current byte of a multi-byte instruction currently being executed. A counter is also coupled between the address bus and the data bus and is additionally coupled to a program register to allow loading of the counter contents into the program register independently of the status of the address bus. An auxiliary register is also coupled between the address bus and the data bus. The counter is updated every machine cycle during execution of the instruction, except for certain instructions during which the counter is inhibited to allow it to function as an auxiliary register, thereby storing the address of the next instruction. For certain instructions, the address bus is utilized for data transfers to or from the auxiliary register simultaneously with loading of the program register from the counter, depending on the type of instruction being executed. The address bus is divided into two sections, each N bits wide, one for transferring higher order address bits and the other for independently transferring lower order address bits. This architecture permits execution of many instructions in fewer machine cycles than was previously possible.
REFERENCES:
patent: 3094610 (1963-06-01), Humphrey, Jr. et al.
patent: 3462744 (1969-08-01), Tomasulo et al.
patent: 3676851 (1972-07-01), Eastman
patent: 3702988 (1972-11-01), Haney et al.
patent: 3737861 (1973-06-01), O'Neill et al.
patent: 3739352 (1973-06-01), Packard
patent: 3757306 (1973-09-01), Boone
patent: 3786436 (1974-01-01), Zelinski et al.
patent: 3820084 (1974-06-01), Jones et al.
patent: 3821715 (1974-06-01), Hoff, Jr. et al.
Bennett Thomas H.
Kouvoussis Anthony E.
Wiles Michael F.
Hoffman Charles R.
Motorola Inc.
Nusbaum Mark E.
LandOfFree
Microprocessor chip register bus structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Microprocessor chip register bus structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microprocessor chip register bus structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-75910