Microprocessor capable of unpacking packed data in response to a

Details Microprocessor capable of unpacking packed data in response to a Microprocessor capable of unpacking packed data in response to a

1999-03-22

2000-09-12

Kim, Kenneth S.

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

712221, 712223, 712225, G06F 930

Patent

active

061192163

ABSTRACT:
A microprocessor capable of unpacking packed data in response to an unpack instruction. The microprocessor having a a storage area to store a first packed data and a second packed data respectively including a first plurality of data elements and a second plurality of data elements, wherein each data element in the first plurality of data elements corresponds to a different data element in the second plurality of data elements, in a respective position. The microprocessor also includes a circuit that simultaneously copies less than all data elements from the first plurality of data elements and corresponding data elements from the second plurality of data elements into a storage area as a third plurality of separate data elements in a third packed data in response to the unpack instruction.

REFERENCES:
patent: 5423010 (1995-06-01), Mizukami
patent: 5625374 (1997-04-01), Turkowski
patent: 5680161 (1997-10-01), Lehman et al.
patent: 5835782 (1998-11-01), Lin et al.
patent: 5862067 (1999-01-01), Mennemeien et al.

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