Microprocessor capable of ensuring flexible recovery time for I/

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395878, 395500, 395550, 364DIG1, 3642715, 3642718, G06F 1314

Patent

active

055555594

ABSTRACT:
A microprocessor which has bus cycles of a memory access operation, an I/O access operation, and an idle state, includes a register for storing the number of the idle states to be inserted when first and second I/O accesses are consecutively executed, and a counter circuit for counting a clock when the first I/O access has been executed. A resetting circuit receives a signal indicating that the last access is the I/O access and resets the counter circuit when the first I/O access has been executed, and a comparator compares an output of the register with an output of the counter circuit for generating a recovery end signal when coincidence is detected. A timing generator generates state signals to the effect that the second I/O access is not executed until the recovery end signal is generated. With the inventive configuration, in the case of consecutive I/O accesses, after completion of a first I/O access, the idle state, in which no bus access is executed, is repeatedly inserted, with the number of idle states being inserted being counted by the counting circuit. The number of repeated idle states counted by the counting circuit is compared with the value stored in the memory and, when coincidence is detected, the recovery end signal is outputted so that a next I/O access is started.

REFERENCES:
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patent: 4631702 (1986-12-01), Korba
patent: 4772888 (1988-09-01), Kimura
patent: 5021985 (1991-06-01), Hu et al.
patent: 5065313 (1991-11-01), Lunsford
patent: 5125088 (1992-06-01), Culley
patent: 5155812 (1992-10-01), Ehlig et al.
patent: 5163135 (1992-11-01), Nakamura
patent: 5220659 (1993-06-01), Larson et al.
Kuwata, Patent Abstracts of Japan, vol. 14, No. 286, p. 99, JP 2-85951 (20 Jun. 1990).

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