Microprocessor capable of decoding two instructions in parallel

Details Microprocessor capable of decoding two instructions in parallel Microprocessor capable of decoding two instructions in parallel

1993-12-17

1995-04-18

Lall, Parshotam S.

Boots, shoes, and leggings

3642328, 3642599, 3642629, 3642656, 3642663, G06F 900, G06F 930

Patent

active

054086256

ABSTRACT:
An instruction fetch unit IU in a microprocessor capable of decoding two instructions in parallel fetches first and second instructions of the shortest instructions in one cycle. The fetched first instruction is supplied to and decoded by a first instruction decoder ID0, while the fetched second instruction is supplied to and decoded by a second instruction decoder ID1. In a case where an instruction having a bit width longer than the shortest instruction has been fetched by the instruction fetch unit IU, information to be decoded by the second instruction decoder ID1 is the non-head code of the instruction, and hence, a pipeline control unit PCNT invalidates the decoded result of the second instruction decoder ID1. Thus, it is permitted to decode the two shortest instructions in parallel, and to eliminate the erroneous information of the decoded result of the second decoder in the case of the fetch of the non-shortest instruction.

REFERENCES:
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patent: 5113503 (1992-05-01), Sasaki et al.
patent: 5148528 (1992-09-01), Fite et al.
patent: 5202967 (1993-04-01), Matsuzaki et al.
Kohn, Leslie, et al. "Session 3: Floating-Point Processors," IEEE International Solid-State Circuits Conference, 1993, pp. 54-55. (English)

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