Microprocessor bus interface unit which changes scheduled data t

Details Microprocessor bus interface unit which changes scheduled data t Microprocessor bus interface unit which changes scheduled data t

1988-08-01

1991-12-17

Lee, Thomas C.

Boots, shoes, and leggings

364DIG1, 3642434, 36492793, 3649278, 364DIG2, G06F 300

Patent

active

050739697

ABSTRACT:
A bus interface unit for a microprocessor which has an internal data bus of n bytes where n is greater than 2 for sensing and responding to enabling signals from external memory circuitry. The microprocessor provides address signals (31) for an n byte transfer (read or write) of data. Input pins receive at least one signal (byte size signal (34 or 35)) which indicates the number of bytes that the memory will transfer on the next ready signal. The microprocessor includes an output line for providing a last signal indicating that a data transfer request by the microprocessor will be satisfied with the data transfer occurring at the next ready signal. Logic circuit (44) is provided in the microprocessor for generating the last signal. This circuit (44) keeps track of the number of bytes that have been transferred, and it periodically senses the byte sizing signals (34 and 35). The logic circuit (44) is able to change the status of the last signal (29) "on the fly". Therefore, by way of example, the external memory can provide a particular byte size signal as a default condition, and then change the signal when the memory determines the number of bytes that the memory is actually able to transfer.

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