Boots – shoes – and leggings
Patent
1991-07-08
1995-08-08
Lee, Thomas C.
Boots, shoes, and leggings
395481, 395856, 395878, 36423223, 3642328, 3642419, G06F 1300, G06F 1338, G06F 1340
Patent
active
054407524
ABSTRACT:
A computer system comprising a microprocessor architecture capable of supporting multiple processors. Data transfers between data and instruction caches, I/O devices, and a memory am handled using a switch network. Access to memory buses is controlled by arbitration circuits which utilize fixed and dynamic priority schemes. A test and set bypass circuit is provided for preventing a loss of memory bandwidth due to spin-locking. A row match comparison circuit is provided for reducing memory latency by giving an increased priority to successive requests for access to memory locations having the same row address. Dynamic switch/port arbitration is provided by changing device priority based on the intrinsic priority of the device, the number of times that a request has been serviced based on a row match, the number of times that a device has been denied service, and the number of times that a device has been serviced.
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Hagiwara Yasuaki
Lau Te-Li
Lentz Derek J.
Nguyen Le Trong
Tang Cheng-Long
Dinh D.
Lee Thomas C.
Seiko Epson Corporation
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