Microprocessor architecture capable of supporting multiple...

Details Microprocessor architecture capable of supporting multiple... Microprocessor architecture capable of supporting multiple...

2005-10-11

2005-10-11

Dinh, Dung C. (Department: 2152)

Electrical computers and digital processing systems: processing

Processing architecture

Distributed processing system

C710S243000

Reexamination Certificate

active

06954844

ABSTRACT:
A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of the processor and the one or more memory ports of the processor. The memory control unit also includes a switch arbitration unit to arbitrate for the switch network, and a port arbitration unit to arbitrate for the one or more memory ports.

REFERENCES:
patent: 4315308 (1982-02-01), Jackson
patent: 4482950 (1984-11-01), Dshkhunian et al.
patent: 4597054 (1986-06-01), Lockwood et al.
patent: 4719569 (1988-01-01), Ludemann et al.
patent: 4829467 (1989-05-01), Ogata
patent: 4916604 (1990-04-01), Yamamoto et al.
patent: 4991081 (1991-02-01), Bosshart
patent: 5089951 (1992-02-01), Iijima
patent: 5097409 (1992-03-01), Schwartz et al.
patent: 5140682 (1992-08-01), Okura et al.
patent: 5148533 (1992-09-01), Joyce et al.
patent: 5222223 (1993-06-01), Webb, Jr. et al.
patent: 5226125 (1993-07-01), Balmer et al.
patent: 5261057 (1993-11-01), Coyle et al.
patent: 5283903 (1994-02-01), Uehara
patent: 5301278 (1994-04-01), Bowater et al.
patent: 5303382 (1994-04-01), Buch et al.
patent: 5430884 (1995-07-01), Beard et al.
patent: 5436869 (1995-07-01), Yoshida
patent: 5440752 (1995-08-01), Lentz et al.
patent: 5471592 (1995-11-01), Gove et al.
patent: 5604865 (1997-02-01), Lentz et al.
patent: 5666494 (1997-09-01), Mote, Jr.
patent: 5754800 (1998-05-01), Lentz et al.
patent: 5941979 (1999-08-01), Lentz et al.
patent: 6219763 (2001-04-01), Lentz et al.
patent: 6272579 (2001-08-01), Lentz et al.
patent: 2002/0059508 (2002-05-01), Lentz et al.
patent: 3931514 (1990-03-01), None
patent: 0 205 801 (1986-12-01), None
patent: 0 214 718 (1987-03-01), None
patent: 0 214 718 (1987-03-01), None
patent: 0 222 074 (1987-05-01), None
patent: 0 222 074 (1987-05-01), None
patent: 0 319 148 (1989-06-01), None
patent: 0 319 148 (1989-06-01), None
patent: 0 348 076 (1989-12-01), None
patent: 55-53722 (1980-04-01), None
patent: 58-178432 (1983-10-01), None
patent: 63-216159 (1988-09-01), None
patent: 64-88761 (1989-04-01), None
patent: 1-183779 (1989-07-01), None
patent: 1-255042 (1989-10-01), None
patent: 2-37592 (1990-02-01), None
patent: 2-71357 (1990-03-01), None
patent: 2-79153 (1990-03-01), None
patent: 2-181855 (1990-07-01), None
patent: 3-127157 (1991-05-01), None
Agarwal, A. et al., “APRIL: A Processor Architecture for Multiprocessing,”Proceedings of the 17th Annual International Symposium on Computer Architecture, IEEE Computer Society Press, pp. 104-114 (1990).
Corsini, P. and Prete, C.A., “Architecture of the MuTeam system,”IEE Proceedings E—Computers And Digital Techniques, The Institution of Electrical Engineers, vol. 134, Part E, No. 5, pp. 217-227 (Sep. 1987).
Earnshaw, W., “The N4—A High Performance Three Dimensional Multiprocessor Computer System,”IRE WESCON Convention Record, vol. 32, No. 29/2, pp. 1-8 (Nov. 1988).
Johnson, M.Superscalar Microprocessor Design, Prentice-Hall, Inc., ISBN 0-13-875634-1, copy of entire book submitted (1991).
Popescu, V. et al., “The Metaflow Architecture,”IEEE Micro, IEEE, pp. 10-13 and 63-73 (Jun. 1991).
Slater, M., “AMD 286ZX Combines 286 and PC System Logic,”Microprocessor Report, vol. 4, No. 17, MicroDesign Resources Inc., p1(4) (Oct. 3, 1990).
Slater, M., “386SL Brings 386 Power to Notebook Computers,”Microprocessor Report, vol. 4, No. 18, MicroDesign Resources Inc., pp. 1 and 10-14 (Oct. 17, 1990).
Weiss, R., “Third-generation RISC processors,”EDN, pp. 96-104, 106 and 108 (Mar. 30, 1992).
Patterson, D.A. and Hennessy, J.L.,Computer Architecture: A Quantitative Approach, Morgan Kaufman Publishers, Inc., ISBN 1-55880-069-8, copy of entire book submitted (1990).
English-Language Abstract of German Patent Publication No. DE 3931514, from Dialog File No. 351: Derwent WPI, 1 page.
English-Language Abstract of Japanese Patent Publication No. 02-071357, from http://www19.ipdl.jpo.go.jp, 2 Pages.

Affiliated with

Also associated with

Rating

Microprocessor architecture capable of supporting multiple... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Microprocessor architecture capable of supporting multiple..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microprocessor architecture capable of supporting multiple... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3469607