Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Reexamination Certificate
1999-10-08
2004-04-27
Jankus, Almis R. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
Reexamination Certificate
active
06727903
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a microprocessor suitable for performing graphics processes, and more particularly to graphics processing apparatus and method using the microprocessor and suitable for transferring graphics data between memories on separate buses.
2. Description of the Related Art
A conventional microprocessor system having two sets of buses, each set for address, data and control signals, is exemplified by Harvard Architecture. This conventional system is designed so as to avoid any contention between an instruction fetch and a data access by separating an instruction bus and a data bus.
Also, LSIs for graphics process are exemplified by a bit map control processor (BMCP) discussed in Toshiba Review 43th volume, 12th issue (1988), pages 932-935. This BMCP has an 8-bit data bus, as a system bus to which a CPU and a system momory are connected, and a 64-bit local memory data bus and a 24-bit address bus independently of the data bus; the address bus and local memory data bus access 8-plane local memories (image memories). Further, with an address latched, the BMCP can access the system memory.
In the Harvard Architecture, the instruction bus and the data bus are dedicated; the Harvard Architecture is totally silent about the concept of using two sets of buses in data access, such as in graphics transfer between a system memory and a frame memory which transfer is performed most frequently among various procedures of the graphics processing.
The BMCP may use two sets of buses in data access, but has only a single address bus; it is unclear from Toshiba Review that two memories can be simultaneously accessed.
Further, in executing a so-called read/modify/write instruction frequently used for graphics processing in which data in a memory address is read and processed and is then written back to the same address, conventional general microprocessors have the following problems.
First of all, in CISC (Complex Instruction Set Computer) type general processors, although a single instruction is capable of describing a read/modify/write operation with memory addresses designated for a source operand and a destination operand of the operation instruction, the length of instruction is necessarily long. Also, it is not clear if it is possible to make the execution without interposing a wait cycle between a read cycle and a write cycle.
In some of exclusive processors for graphics process, though a read/modify/write instruction can be executed in two successive memory cycles, its modifying function is limited.
In RISC (Reduced Instruction Set Computer) type processors, instructions are basically of a fixed length, and operands accessible to a memory are allowed to be designated only for a load instruction and a store instruction. Thus, execution of a read/modify/write operation requires three instructions, i.e. load, operation and store instructions, failing to execute the load and store instructions in two successive memory cycles.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to enable a high-speed transfer of graphics data between two memories, as accessed simultaneously to the memories on separate buses, in a graphics processing apparatus for processing a large quantity of graphics data.
Another object of the invention is to enable the execution of a read/modify/write operation very popular in graphics processing, without interposing a null cycle between a read cycle and a write cycle, in a processor of RISC-type.
According to a first aspect of this invention, a graphics processing apparatus includes a CPU and a system memory, each connected to a system bus composed of address, data and control buses; a local memory and a frame memory, each connected to a local bus composed of address, data and control buses; and a graphics processing processor having a first port connected to said system memory, and a second port connected to said local bus, said graphics processing processor being capable of simultaneously accessing to the system memory and the local or frame memory via the first and second ports, respectively.
According to a second aspect of the invention, another graphics processing apparatus includes a CPU and a first memory, each connected to a system bus composed of address, data and control buses; a second memory connected to a local bus composed of address, data and control buses; and a graphics processing processor having a first port connected to the system bus, a second port connected to the local bus, and a plurality of internal registers, the graphics processing processor is capable of loading graphics data to one of the internal registers from one of said first and second memories via the corresponding one of the first and second ports and also, in parallel with the loading, capable of storing data to the other one of the first and second memories from another of the internal registers.
According to a third aspect of the invention, a graphics processing method using a graphics processing apparatus includes the steps of: storing a graphics transfer program in the system memory or the local memory, and also storing various graphic data in the system memory; writing a leading address of the graphics transfer program and a leading address of parameters of the graphic data in the system memory or the local memory by the CPU when the graphics data in the system memory are transferred to the frame memory; and causing the graphics processor, according to said graphic transfer program and the parameters, to transfer the graphic data on the system memory to the frame memory via said first and second ports.
According to a fourth aspect of the invention, another graphics processing method using a graphics processing apparatus includes the steps of: storing various graphics drawing programs in the system memory or the local memory; when drawing the graphics, preparing a work list, composed of a leading address of the graphics drawing programs and a leading address of parameters of the graphic data, in the system memory or the local memory by the CPU; and causing the graphics processing processor to read the contents of the work list in response to an instruction of the CPU and to draw the graphics in the frame memory according to the graphics drawing programs and parameters designated by the work list.
According to a fifth aspect of the invention, a microprocessor includes: a processor unit for decoding and executing an instruction; two ports each for transferring address, data and control signals between each of the ports and a respective memory; an address buffer writable from the processor unit and readable from the two ports; a data buffer which is readable and writable from the two ports and from which an instruction may be read by the processor unit; and means for controlling an address transfer from the address buffer to one of the memories and also a data transfer between the data buffer and one of the memories via the designated port according to a memory access request and a port designating signal from the processor unit; whereby an instruction fetch and a data access can be performed with respect to the two memories.
According to a sixth aspect of the invention another microprocessor includes: a processor unit for decoding and executing an instruction; two ports each for transferring address, data and control signals between each of the ports and a respective memory; two sets of an address buffer and a data buffer, each of the sets dedicated for a respective one of the two ports; means for managing the operation of each of the two ports; and means for writing, to a register in said processor unit, data read from the memories; whereby accesses can be taken simultaneously to two memories via said two ports.
According to a seventh aspect of the invention, still another microprocessor for executing instructions each having a fixed length, includes first instruction holding means for holding a primary instruction read from a program; second instruction holding means for holding a sub-instruc
Fukushima Tadashi
Komagawa Tooru
Matsuo Shigeru
Miyamoto Takashi
Yamada Hiromichi
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Jankus Almis R.
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