Micropower, minimal area DC sensing power-up reset circuit

Details Micropower, minimal area DC sensing power-up reset circuit Micropower, minimal area DC sensing power-up reset circuit

1999-08-03

2001-03-20

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S198000

Reexamination Certificate

active

06204704

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to power-up reset (PUR) circuits and, in particular, to micropower, minimal area DC sensing PUR circuits for use in monolithic CMOS-based integrated circuits (ICs).
2. Description of the Related Art
For many types of integrated circuits (ICs), power is applied to a sleeping or unpowered IC during a “power-up” phase, during which the power supply V
DD
increases from 0V to a maximum V
M
(i.e., the normal operating value of V
DD
). During this phase, it is often desirable to reset certain circuit elements, such as logic flip-flops and memory shift registers, to some predetermined initial state, to initialize the IC, until the power supply voltage V
DD
reaches a sufficient level for reliable operation. In order to do this, it is desirable to have a reset signal generated (RST or, for active-low designs, RSTN) during the power-up phase. The reset signal is applied to appropriate control inputs of various circuit elements to keep them in an initial or reset state until the reset signal changes upon the supply voltage reaching a certain threshold. In this manner, various circuit elements of the IC start operation in a predictable state and after a sufficient supply voltage is present.
Power-up reset (PUR) circuits are typically utilized to generate this reset signal. A PUR circuit supplies a reset voltage signal to the various circuit elements, and is coupled to the V
DD
power supply rail, as are other components of the IC. The reset signal (RST or RSTN, depending on whether the PUR circuit is active high or low in design) is output on a output terminal or line of the PUR circuit. PUR circuits often comprise complementary metal-oxide semiconductor (CMOS) fabricated components, such as CMOS field-effect transistors (CMOS FETs). Digital signals in such systems typically represent a bit of data, that is, a logic−0 or logic−1, sometimes referred to as low or high, respectively, corresponding to the low voltage state (typically V
ss
, e.g. ground=0V)) or the high voltage state (typically V
DD
, e.g. 3-5V, or some other intermediate value while V
DD
is ramping up). Thus, the reset signal may have either a high state or low state at any time. The reset signal may be active high or active low, which determines whether the high state or the low state, respectively, is considered to be “asserting” the reset signal.
It is generally desirable for the PUR circuit to be formed on the IC chip having the circuit elements requiring initialization. However, this requires that some of the IC area be devoted to the PUR circuit instead of other components. It is therefore also desirable to have the PUR circuit occupy as little area on the chip as possible. It is also often desirable to have the PUR circuit draw as small a current as possible during operation. For example, it may be desirable to achieve micropower operation of the PUR circuit, i.e. to have the PUR circuit draw less than 1&mgr;A of DC current during operation.
Unfortunately, conventional micropower DC sensing PUR circuits typically have at least three DC paths and thus can require a prohibitively large amount of IC area. Referring now to
FIG. 1
, there is shown a circuit diagram of a conventional DC sensing PUR circuit
100
. PUR circuit
100
is coupled to power supply rail terminals V
DD
and V
SS
, and outputs an active-low reset signal RSTN at an output terminal or node when a sufficient DC level of V
DD
is sensed by circuit
100
. Although PUR circuit
100
can be configured for micropower operation, it has three DC paths (currents I
DC1
, I
DC2
, and I
DC3
) and thus requires a large amount of area for the transistors M
1
and M
4
and the two resistors R
1
, R
2
to achieve micropower operation.
Another type of PUR circuit is the transient sensing PUR circuit. Referring now to
FIG. 2
, there is shown a simplified circuit diagram of a conventional transient sensing PUR circuit
200
. PUR circuit
200
comprises only two inverters I
1
, I
2
, one resistor R
1
, and one capacitor C
1
. Such transient PUR circuits do not require as much IC area because they do not have DC paths and thus do not require as many components or elements. Instead, such transient sensing PUR circuits are sensitive to the V
DD
ramp rate as well as the DC level of the V
DD
power supply. Micropower operation can be achieved because there are no DC paths. Unfortunately, because PUR circuit
200
is sensitive to the V
DD
ramp rate in addition to its level, it is subject to unpredictable behavior and thus is not as robust as typical DC sensing PUR circuits. A marginal increase in robustness requires a large increase in complexity, and thus, cost and IC area.
Accordingly, there is a need for a robust micropower PUR circuit which requires a comparatively small amount of IC area.
SUMMARY
An integrated circuit comprising a DC sensing power-up reset (PUR) circuit and method for generating a reset signal. The PUR circuit comprises a first terminal for receiving a supply voltage and a second terminal for receiving a reference voltage corresponding to a low logic state. A first transistor is coupled between the first terminal and a first node, wherein the first transistor switches on when the supply voltage is rising and exceeds a rising trip point voltage. A second transistor is coupled between the first terminal and the first node, and switches off when the supply voltage falls below a falling trip point voltage which is less than the rising trip point voltage. A first inverter is coupled at an input terminal to the first node and at an output terminal to a second node. A resistor is coupled between the first node and the second terminal. The resistor pulls the first node down to the reference voltage while the first and second transistors are both off and limits current flowing through the first and second transistors while either or both of the first and second transistors is on.


REFERENCES:
patent: 5073874 (1991-12-01), Yamada et al.
patent: 5111067 (1992-05-01), Wong et al.
patent: 5767710 (1998-06-01), Cho
patent: 5942925 (1999-08-01), Stahl
patent: 6052006 (2000-04-01), Talaga, Jr. et al.

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