Microinstruction sequencer for instructing arithmetic, logical a

Details Microinstruction sequencer for instructing arithmetic, logical a Microinstruction sequencer for instructing arithmetic, logical a

1987-07-02

1990-01-02

Zache, Raulfe B.

Boots, shoes, and leggings

3642446, 3642628, 3642597, 3642633, G06F 922

Patent

active

048917540

ABSTRACT:
A microinstruction sequencer capable of directing an arithmetic-logic unit to conduct conditional operations is disclosed and generally includes a ROM and a selection circuit. The ROM has a memory of m bits wide and n words long, wherein for an m bit wide word in the ROM which defines a conditional operation, a first plurality of bits of the m bits are allocated to a first set of bits for instructing the arithmetic-logic unit as to the function it is to perform, a second plurality of bits of the m bits are allocated to a second set of bits for instructing the arithmetic-logic unit as to the function it is to perform, and a third plurality of bits of the m bits are allocated to a set of control bits. The selecting circuit selects one set of bits from at least the first and second set of bits, and includes a controller for receiving the control bits and controlling the selection by the selection circuit in response thereto. By selecting between the first and second sets of bits, the microinstruction sequencer conditionally instructs the arithmetic-logic unit.

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patent: 4615004 (1986-09-01), Chevillat et al.
patent: 4800486 (1989-01-01), Horst et al.

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