Microinstruction processing unit responsive to interruption prio

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G06F 922

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active

043386628

ABSTRACT:
A microinstruction processing unit of the type in which microinstructions are fed and executed in a predetermined sequence to process data in a data processing system in which, upon the feeding of a higher priority microinstruction, the execution of a lower priority microinstruction is interrupted but is subsequently carried out. Microinstructions lower than the highest priority rank are supplied to control the transfer of data to and from a storage register and to and from a priority rank designated position in a register file. Upon the interruption by has higher priority ranking microinstruction, the data for an interrupted microinstruction remains in the register file but it is replaced in the storage register by data the higher priority ranking microinstruction. Signals representing the priority ranking of the interrupted microinstructions are stored in a stacking type previous level register and after an interruption, the signals from the previous level register are fed to a multiplexer to control the transfer of data from the register file to the storage register.

REFERENCES:
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patent: 3781810 (1973-12-01), Downing
patent: 4017839 (1977-04-01), Calle et al.
patent: 4103328 (1978-07-01), Dalmasso
patent: 4103330 (1978-07-01), Thacker
Richard W. Watson, Timesharing System Design Concepts, (McGraw-Hill, 1970), Chapter 4, "Protection and Control", pp. 111-131.
IBM Corp., A Guide to IBM System/7, (First Edition, Oct. 1970), pp. 24-25 and preface.
Samir S. Husson, Microprogramming Principles and Practices, (Prentice-Hall, 1970), pp. 219-222.
Texas Instruments, Inc., The TTL Data Book for Design Engineers, (2nd Edition, 1976), pp. 7-151 through 7-157.
Texas Instruments, Inc., The TTL Data Book for Design Engineers, (1st Edition, 1973), pp. 527-528.

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