Boots – shoes – and leggings
Patent
1980-02-07
1983-01-04
Shaw, Gareth D.
Boots, shoes, and leggings
G06F 900, G06F 922, G06F 700
Patent
active
043675247
ABSTRACT:
An execution unit which is part of a general-purpose microprocessor, partitioned between two integrated circuit chips, with the execution unit on one chip and an instruction unit on another chip. The execution unit provides the interface for accessing a main memory to thereby fetch data and macroinstructions for transfer to the instruction unit when requested to do so by the instruction unit. The execution unit receives arithmetic microinstructions in order to perform various arithmetic operations, and receives access-memory microinstructions in order to develop memory references from logical addresses received from the instruction unit. Arithmetic operations are performed by a data manipulation unit which contains registers and arithmetic capability, controlled by a math sequencer. Memory references are performed by a reference-generation unit which contains base-and-length registers and an arithmetic capability to generate and check addresses for referencing an off-chip main memory, and is controlled by an access sequencer.
REFERENCES:
patent: 3302183 (1967-01-01), Bennett et al.
patent: 3878514 (1975-04-01), Faber
patent: 4008642 (1977-02-01), Kanda
patent: 4079455 (1978-03-01), Ozga
Budde David L.
Colley Stephen R.
Domenik Stephen L.
Goodman Allan L.
Howard James D.
Intel Corporation
Lamb Owen L.
Mills, III John G.
Shaw Gareth D.
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