Microelectronics unit mounting with multiple lead bonding

Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement

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174251, 174254, 174256, 174267, 361749, 361776, 439 67, 439 77, H05K 100

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active

054553903

ABSTRACT:
A component for mounting semiconductor chips or other microelectronic units includes a flexible top sheet with an array of terminals on it, and with flexible leads extending downwardly from the terminals. A compliant dielectric support layer surrounds the leads, holding the lead tips in precise locations. The leads are desirably formed from wire such as gold wire, and have eutectic bonding alloy on their tips. The component can be laminated to a chip or other unit under heat and pressure to form a complete subassembly with no need for individual bonding to the contacts of the chip. The subassembly can be tested readily and provides compensation for thermal expansion.

REFERENCES:
patent: 3373481 (1968-03-01), Lins et al.
patent: 3795037 (1974-03-01), Luttmer
patent: 3811186 (1974-05-01), Larnerd et al.
patent: 4067104 (1978-01-01), Tracy
patent: 4142288 (1979-03-01), Flammer et al.
patent: 4326663 (1982-04-01), Oettel
patent: 4447857 (1984-05-01), Marks et al.
patent: 4520562 (1985-06-01), Sade et al.
patent: 4629957 (1986-12-01), Walters et al.
patent: 4661192 (1987-04-01), McShaen
patent: 4667219 (1987-05-01), Lee et al.
patent: 4785137 (1988-11-01), Samuels
patent: 4793814 (1988-12-01), Zifcak et al.
patent: 4893172 (1990-01-01), Matsummoto et al.
patent: 4926241 (1990-05-01), Carey
patent: 4949158 (1990-08-01), Ueda
patent: 4954877 (1990-09-01), Nakanishi et al.
patent: 4954878 (1990-09-01), Fox et al.
patent: 4955523 (1990-09-01), Calomagno et al.
patent: 5047830 (1991-09-01), Grabbe
patent: 5049085 (1991-09-01), Reylek et al.
patent: 5067007 (1991-11-01), Kanji et al.
patent: 5072289 (1991-12-01), Sugimoto et al.
patent: 5131852 (1992-07-01), Grabbe et al.
patent: 5148265 (1992-09-01), Khandros et al.
patent: 5148266 (1992-09-01), Khandros et al.
patent: 5152695 (1992-10-01), Grabbe et al.
patent: 5173055 (1992-12-01), Grabbe
patent: 5197892 (1993-03-01), Yoshizawa et al.
patent: 5230931 (1993-07-01), Yanizaki et al.
patent: 5254811 (1993-11-01), Ludden et al.
patent: 5258330 (1993-11-01), Khandros et al.
"Method of Testing Chips and Joining Chips to Substrates", Research Disclosure, Feb. 1991, No. 322, Kenneth Mason Publication Ltd., England.

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