Microelectronic shadow masking process for reducing punchthrough

Details Microelectronic shadow masking process for reducing punchthrough Microelectronic shadow masking process for reducing punchthrough

1981-10-14

1983-07-19

Roy, Upendra

Metal treatment

Compositions

Heat treating

29571, 29576B, 148187, 357 23, 357 91, B01J 1700, H01L 21265

Patent

active

043941826

ABSTRACT:
A process for forming a doped region in a substrate which is in alignment with a circuit member by forming a masking member on a layer, the masking member defining the outline on the circuit member; and etching the layer employing the masking member as a mask to define the circuit member, the etching continuing such that the circuit member includes sloping side faces. Subsequently, a dopant species is implanted into the substrate so as to form the doped region, the dosage and energy of ions implanted being selected such that ions are partially blocked by the portion of the circuit member beneath the sloping side faces thereby providing a more lightly doped and more shallow distribution of implanted species region than in other regions.

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W. G. Oldham and E. Hieke, IEEE Electron Device Letters, vol. EDL-1, No. 10, Oct. 1980, p. 217, "A High Resolution Negative Electron Resist by Image Reversal".

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