Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Patent
1996-05-29
1998-08-11
Jackson, Jerome
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
257723, 257724, H01L 2348, H01L 2352, H01L 2940
Patent
active
057931160
ABSTRACT:
Microelectronic packages are formed wherein solder bumps on one or more substrates are expanded, to thereby extend and contact the second substrate and form a solder connection. The solder bumps are preferably expanded by reflowing additional solder into the plurality of solder bumps. The additional solder may be reflowed from an elongated, narrow solder-containing region adjacent the solder bump, into the solder bump. After reflow, the solder bump which extends across a pair of adjacent substrates forms an arched solder column or partial ring of solder between the two substrates.
REFERENCES:
patent: 3501681 (1970-03-01), Weir
patent: 3663184 (1972-05-01), Wood et al.
patent: 3760238 (1973-09-01), Hamer et al.
patent: 3770874 (1973-11-01), Krieger et al.
patent: 3871014 (1975-03-01), King et al.
patent: 3942187 (1976-03-01), Gelsing et al.
patent: 4074342 (1978-02-01), Honn et al.
patent: 4113578 (1978-09-01), Del Monte
patent: 4855809 (1989-08-01), Malhi et al.
patent: 4948754 (1990-08-01), Kondo et al.
patent: 4950623 (1990-08-01), Dishon
patent: 4962058 (1990-10-01), Cronin et al.
patent: 5113314 (1992-05-01), Wheeler et al.
patent: 5160409 (1992-11-01), Moore et al.
patent: 5162257 (1992-11-01), Yung
patent: 5194137 (1993-03-01), Moore et al.
patent: 5250843 (1993-10-01), Eichelberger
patent: 5293006 (1994-03-01), Yung
patent: 5327013 (1994-07-01), Moore et al.
patent: 5327327 (1994-07-01), Frew et al.
patent: 5347428 (1994-09-01), Carson et al.
patent: 5354711 (1994-10-01), Heitzmann et al.
patent: 5406701 (1995-04-01), Pepe et al.
patent: 5424920 (1995-06-01), Miyake
patent: 5432729 (1995-07-01), Carson et al.
patent: 5453582 (1995-09-01), Amano et al.
patent: 5616962 (1997-04-01), Ishikawa et al.
Howell et al., "Area Array Solder Interconnection Technology for the Three-Dimensional Silicon Cube", Proceedings of the 1995 45th Electronic Components & Technology Conference, pp. 1174-1178.
Lineback, "3D IC Packaging Moves Closer to Commercial Use", Electronic World News, May 21, 1990, p. 15.
Deane Philip A.
Rinne Glenn A.
Clark S. V.
Jackson Jerome
MCNC
LandOfFree
Microelectronic packaging using arched solder columns does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Microelectronic packaging using arched solder columns, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microelectronic packaging using arched solder columns will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-392025