Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
1998-09-18
2002-01-01
Potter, Roy (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S612000
Reexamination Certificate
active
06335222
ABSTRACT:
BACKGROUND OF THE INVENTION
Microelectronic elements such as semiconductor chips have been connected to circuit panels by soldering. One technique which has been utilized heretofore is referred to as “flip chip” bonding. In flip chip bonding, the front surface of the chip bearing the contact pads of the chip faces downwardly, towards the surface of a circuit panel having a pattern of pads matching the pattern of the contact pads on the chip. The pads on the chip are bonded to the mating pads on the substrate. In one variant of this technique, referred to as a “controlled collapse chip connection” or “C4” bond, individual masses of solder are provided on the contact pads of the chip or substrate prior to assembly. In the assembly process, these masses are reflowed by bringing them to an elevated temperature sufficient to melt or partially melt the solder constituting the masses. The assembly is then cooled, leaving each contact pad on the chip connected to the corresponding contact pad on the circuit panel by a mass of solid solder. As described, for example, in
Multi-Chip Module Technologies And Alternatives: The Basics, Doane and Franzon, Editors
(1993), pp. 468-471, surface tension in the molten solder tends to form each solder mass into a generally barrel-shaped object having narrow neck portions at the junctures between the solder masses and the contact pads on the chip and circuit panel.
The solder bonds in such assemblies typically are subjected to thermal fatigue stress during manufacture and during use of the assembly. The electrical power dissipated within the chip and other elements of the assembly tends to heat the chip and the circuit panel, so that the temperatures of the chip and circuit panel rise and fall depending on use of the device. Processing operations during manufacturing also cause the temperature of the assembly to rise and fall. As the chip and substrate ordinarily are formed from different materials having different coefficients of thermal expansion, the chip and the circuit panel ordinarily expand and contract by different amounts. Even where the chip and circuit panel are formed from materials having the same coefficients of thermal expansion, differential expansion and contraction still can occur because the elements of the assembly tend to heat and cool at different rates. For example, the temperature of the chip typically increases more rapidly than the temperature of the circuit panel when power is first applied to the chip. Differential expansion and contraction causes the contact pads on the chip to move relative to the contact pads on the substrate, which in turn tends to strain the solder bonds. The barrel-shaped solder bonds resulting from conventional C4 bonding techniques are susceptible to failure under these conditions. In particular, the narrow necks of the solder masses interfaces with the contact pads, produce stress concentrations at highly stressed regions of the solder bonds.
As described in the aforementioned
Doane and Franzon
treatise, attempts have been made to alleviate these problems by changing the shapes of the solder masses so as to provide elongated solder masses having narrow sections midway between the contact pads of the chip and circuit panel. As described, for example, in Lakritz et al., U.S. Pat. No. 4,545,610 and Agarwala, et al., U.S. Pat. No. 5,130,779, elongated solder columns can be formed by using multiple solder masses stacked above one another with separate elements to maintain the chip and circuit panel at the desired spacing during the reflow process. As described in Schmidt, et al., U.S. Pat. No. 5,148,968 and Latta, U.S. Pat. No. 5,385,291, elongated solder columns can also be made by pulling the chip and circuit panel away from one another while the components are at an elevated temperature in the reflow operation. The Latta '291 patent suggests that the step of moving the elements of the assembly be conducted under an elevated pressure applied by increasing the atmospheric pressure around the assembly which allegedly results in a different wall configuration.
Other assemblies incorporating elongated solder columns are disclosed in Flip Chip Technology 1994 Update U.S. Patents, International Interconnection Intelligence, pp. 4-2 reporting IBM Technical Disclosure Bulletin, Vol. 36, No. 1, p. 174, January 1993; in IBM Technical Disclosure Bulletin, Vol. 27, No. 8, January 1985 entitled Solder-Filled Elastomeric Spacer; and in U.S. Pat. Nos. 4,581,680 and 4,967,950.
Chip mounting procedures using elongated solder columns heretofore have suffered form considerable drawbacks. These procedures require specialized techniques and considerable care during mounting of the chip to the circuit panel. Moreover, these procedures require handling and testing of bare, unpackaged semiconductor chips. It is difficult to test such a bare chip prior to attachment of the chip to the circuit panel. Moreover, the bare chip is susceptible to damage during handling and testing.
As shown in the preferred embodiments of commonly assigned U.S. Pat. Nos. 5,148,265; 5,148,266; 5,455,390, 5,518,964 5,688,716 and 5,798,286 as well as in co-pending, commonly assigned U.S. patent applications Ser. No. 08/653,016 filed May 24, 1996; Ser. No. 08/678,808 filed Jul. 12, 1996, the disclosures of which are all incorporated by reference herein, it is desirable to provide interconnections between the contacts on a chip and external circuitry by providing a further dielectric element, commonly referred to as a “interposer” or “chip carrier” having terminals. The dielectric element is juxtaposed with the chip and the terminals on the dielectric element are connected to the contacts on the chip, desirably by flexible leads extending between the interposer and the chip. The terminals on the dielectric element may be connected to a substrate such as a circuit panel, as by solder bonding the terminals to contact pads of the substrate. The dielectric element remains movable with respect to the chip so as to compensate for thermal expansion and contraction of the components. That is, various parts of the chip can move with respect to the dielectric element and with respect to the terminals on the dielectric element, as the components expand and contract. In a particularly preferred arrangement, a compliant dielectric layer is incorporated in the dielectric element or provided as a separate component so that the compliant layer lies between the chip and the terminals. The compliant layer may be formed from a material such as a gel, elastomer, foam or the like. The compliant layer mechanically decouples the dielectric element and terminals from the chip and facilitates movement of the dielectric element and terminals relative to the chip. The compliant layer may also permit movement of the terminals in the Z direction, towards the chip, which further facilitates testing and mounting of the assembly. Thus, differential thermal expansion and contraction of the circuit panel and chip does not cause fatigue failures of the solder bonds. In a variant of this approach, disclosed in commonly assigned PCT International Publication WO 97/40958, the disclosure of which is also incorporated by reference herein, the terminals on the interposer can be connected to the contacts of the chip by masses of a low-melting electrically conductive composition which liquefies at the temperatures attained during service. The compliant layer retains the liquid in place, so that masses of conductive liquid provide deformable connections between the chip and interposer. As further disclosed in these patents and patent applications, one or more chips may be mounted to a common dielectric element or interposer, and additional circuit elements may also be to such a dielectric element. The dielectric element may incorporate conductive traces which form interconnections between the various chips and electronic components of the assembly and which completes circuits as required.
In these techniques, the assembly of the chip and the interposer, with the terminals thereon prov
Lerner David Littenberg Krumholz & Mentlik LLP
Potter Roy
Tessera Inc.
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