Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step
Reexamination Certificate
1999-05-05
2001-09-25
Picardat, Kevin M. (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Including adhesive bonding step
C438S110000, C438S108000
Reexamination Certificate
active
06294407
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to microelectronic devices and fabrication methods, and more particularly to microelectronic packages and fabrication methods.
BACKGROUND OF THE INVENTION
Advances in semiconductor fabrication technology have allowed Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI) integrated circuits, having up to several million devices thereon, to be reliably and economically produced. As device densities increase and device sizes shrink, system performance often becomes more limited by the interconnection and packaging of the integrated circuits, and not by the internal circuitry of the integrated circuits themselves. For example, package limitations such as the maximum allowed number of input/output pads may result in the inability to utilize all of the integrated circuit's capabilities. Multi-chip packaging may require wide spacing of integrated circuits to accommodate wiring channels, which may result in longer wiring distances for integrated circuit interconnection, and may lead to increased parasitic capacitance and a decrease in system speed. Moreover, complex packaging structures may be expensive and unreliable.
Printed circuit board (PCBs) are widely used substrates for interconnecting Integrated Circuit (IC) chips and various other components which can make up electrical systems. Packaged chips and other devices are typically picked and placed onto the surface of a PCB and electrical connections are then made by reflowing low temperature (Eutectic) solders between the outer leads of the IC chip package and pads on the surface of the PCB. This “Surface Mount” PCB technology has been successfully utilized for many years to build up all but the most exotic electronic systems and at the present time may still represent the most common PCB technology currently practiced.
The PCB itself originally was developed to eliminate the need to wire electrical components together with individual wires. Individual wiring generally is a time consuming and thereby expensive process for all but the simplest of electronic systems. The first systems built on PCBs used discrete electronic components such as individual resistors, capacitors etc. utilizing through-hole technology. With the advent of the IC, the interconnect demand on PCBs significantly increased due to the need to connect the multiple small Input/Output terminals of a packaged IC. Through-hole IC carriers (single and dual-in line packages) generally replaced the lead wires of discrete components and were passed through the PCB and soldered from the backside of the board, similar to the manner of soldering the discrete component wire leads. Surface mount technology, wherein the leads of an IC carrier are connected at the front surface, eliminated the need for the through-holes and conserved internal PCB active interconnect area.
Unfortunately, it may be difficult to economically build additional layers of printed wiring to support the interconnects that are desired for advanced ICs. Moreover, shrinking the wiring patterns and/or increasing the number of layers of the board to increase interconnect density may be increasingly difficult and costly to accomplish with traditional PCB technology. High end and highly miniaturized systems also have been built utilizing complex and expensive ceramic and composite substrates. Ceramic Multi-Chip-Module (MCM) technology is an example of an alternative packaging technology. These types of packages may not be economically viable for low cost consumer electronic systems.
Several other technologies for extending PCB technology without completely changing (i.e. to ceramic instead of fiberglass/epoxy) the basic material set (organic dielectric/copper conductor) are being investigated. These types of approaches include DYCO strate/MicroVia (see www.dyconex.com), Surface Laminated Circuit Boards (SLC-See U.S. Pat. No. 5,766,825 to Shirai et al.) and Flex Patches on Board (see U.S. Pat. No. 5,719,749 to Stopperan et al.). Adding thin film interconnect by directly processing it on the surface a PCB also is being explored.
With the exception of Flex Patches on Board, wherein a patch of flexible interconnect is transferred to the surface of the board, radical changes in the way a substrate is processed may be required by the PCB manufacturer to achieve these technologies. Radical departure from the basic PCB technology may require a long and costly development effort on the part of PCB manufacturers to implement. Moreover, the increase in interconnect density may be incremental. For example, geometries may remain above micron range pitches—they may remain in the mil range. Furthermore, the cost of producing these substrates may remain high.
Unfortunately, accomplishing fine line lithography with the basic PCB material set may be a difficult task for several reasons. First, unlike silicon wafers, the PCB may be far from an ideal substrate for the production of fine line wiring. Moreover, unlike the IC industry that uses 6″, 8″ and 12″ or larger standard wafer formats, standard equipment to directly produce fine line wiring on PCBs does not appear to be available.
The above survey indicates that there continues to be a need for packaging technology that can provide high density at low cost and that need not have an appreciable effect on the standard processing PCBs, so that the basic PCB technology may be extended.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved microelectronic packages and methods of fabricating the same.
It is another object of the present invention to provide microelectronic packages that can allow high density wiring to be used with conventional printed circuit boards.
It is still another object of the present invention to provide microelectronic packaging and fabrication methods that can allow conventional printed circuit board technology to be extended to high performance and/or high density microelectronic systems.
These and other objects can be provided, according to the present invention, by providing a thin film decal and a dielectric adhesive layer that includes a plurality of conductive vias therein, between a first level microelectronic substrate and a second level microelectronic substrate. The combination of the thin film decal and the dielectric adhesive layer including a plurality of conductive vias therein can provide an interconnect packaging technology that can be low cost and/or high density, and can be used in conjunction with printed circuit boards that are produced by standard board process technology. The capabilities of printed circuit board technology therefore can be extended.
More specifically, microelectronic packages according to the present invention comprise a first level substrate including a plurality of microelectronic devices and a plurality of first level substrate input/output pads on a face thereof. The first level substrate may be an integrated circuit. A thin film decal is on the face of the first level substrate. The thin film decal includes first and second opposing faces. A plurality of first decal input/output pads are on the first face, at least one of which is electrically connected to at least one of the first level substrate input/output pads. A plurality of second decal input/output pads are on the second face. At least one internal wiring layer in the thin film decal is electrically connected to at least one of the first and second decal input/output pads. A second level substrate including a plurality of second level substrate input/output pads on a face thereof also is provided. The second level substrate may be a printed circuit board.
According to the invention, a dielectric adhesive layer is provided that is adhesively bonded to the thin film decal and that also is adhesively bonded to the second level substrate. The dielectric adhesive layer includes a plurality of conductive vias therein that electrically connect at least one of the second level substrate input/output pads to at least one of the
Collins D. M.
Daniels & Daniels, P.A.
Picardat Kevin M.
Virtual Integration, Inc.
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