Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
2000-12-15
2003-04-29
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S712000, C257S787000, C257S701000
Reexamination Certificate
active
06555906
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to apparatus and processes for the fabrication of a microelectronic device. In particular, the present invention relates to a fabrication technology that encapsulates at least one microelectronic die and provides a laminated interconnection layer for achieving electronic contact therewith.
2. State of the Art
Higher performance, lower cost, increased miniaturization of integrated circuit components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. As these goals are achieved, microelectronic dice become smaller. Of course, the goal of greater packaging density requires that the entire microelectronic die package be equal to or only slightly larger (about 10% to 30%) than the size of the microelectronic die itself. Such microelectronic die packaging is called a “chip scale packaging” or “CSP”.
As shown in
FIG. 35
, true CSP involves fabricating build-up layers directly on an active surface
404
of a microelectronic die
402
. The build-up layers may include a dielectric layer
406
disposed on the microelectronic die active surface
404
. Conductive traces
408
may be formed on the dielectric layer
406
, wherein a portion of each conductive trace
408
contacts at least one contact
412
on the active surface
404
. External contacts, such as solder balls or conductive pins for contact with an external component (not shown), may be fabricated to electrically contact at least one conductive trace
408
.
FIG. 35
illustrates the external contacts as solder balls
414
, which are surrounded by a solder mask material
416
on the dielectric layer
406
. However, in such true CSP, the surface area provided by the microelectronic die active surface
404
generally does not provide enough surface for all of the external contacts needed to contact the external component (not shown) for certain types of microelectronic dice (e.g., logic).
Additional surface area can be provided through the use of an interposer, such as a substrate (substantially rigid material) or a flex component (substantially flexible material).
FIG. 36
illustrates a substrate interposer
422
having a microelectronic die
424
attached to and in electrical contact with a first surface
426
of the substrate interposer
422
through small solder balls
428
. The small solder balls
428
extend between contacts
432
on the microelectronic die
424
and conductive traces
434
on the substrate interposer first surface
426
. The conductive traces
434
are in discrete electrical contact with bond pads
436
on a second surface
438
of the substrate interposer
422
through vias
442
that extend through the substrate interposer
422
. External contacts
444
(shown as solder balls) are formed on the bond pads
436
. The external contacts
444
are utilized to achieve electrical communication between the microelectronic die
424
and an external electrical system (not shown).
The use of the substrate interposer
422
requires a number of processing steps. These processing steps increase the cost of the package. Additionally, even the use of the small solder balls
428
presents crowding problems which can result in shorting between the small solder balls
428
and can present difficulties in inserting underfill material between the microelectronic die
424
and the substrate interposer
422
to prevent contamination and provide mechanical stability. Furthermore, current packages may not meet power delivery requirements for future microelectronic dice
424
due to thickness of the substrate interposer
422
, which causes land-side capacitors to have too high an inductance.
FIG. 37
illustrates a flex component interposer
452
wherein an active surface
454
of a microelectronic die
456
is attached to a first surface
458
of the flex component interposer
452
with a layer of adhesive
462
. The microelectronic die
456
is encapsulated in an encapsulation material
464
. Openings are formed in the flex component interposer
452
by laser ablation through the flex component interposer
452
to contacts
466
on the microelectronic die active surface
454
and to selected metal pads
468
residing within the flex component interposer
452
. A conductive material layer is formed over a second surface
472
of the flex component interposer
452
and in the openings. The conductive material layer is patterned with standard photomask/etch processes to form conductive vias
474
and conductive traces
476
. External contacts are formed on the conductive traces
476
(shown as solder balls
248
surrounded by a solder mask material
482
proximate the conductive traces
476
).
The use of a flex component interposer
452
requires gluing material layers which form the flex component interposer
452
and requires gluing the flex component interposer
452
to the microelectronic die
456
. These gluing processes are relatively difficult and increase the cost of the package. Furthermore, the resulting packages have been found to have poor reliability.
Therefore, it would be advantageous to develop new apparatus and techniques to provide additional surface area to form traces for use in CSP applications, which overcomes the above-discussed problems.
REFERENCES:
patent: 5353498 (1994-10-01), Fillion et al.
patent: 5422513 (1995-06-01), Marcinkiewicz et al.
patent: 5497033 (1996-03-01), Fillion et al.
patent: 5527741 (1996-06-01), Cole et al.
patent: 5703400 (1997-12-01), Wojnarowski et al.
patent: 5745984 (1998-05-01), Cole, Jr. et al.
patent: 5998859 (1999-12-01), Griswold
patent: 6091250 (2000-07-01), Wood et al.
patent: 11045955 (1999-02-01), None
patent: 11312868 (1999-11-01), None
Towle Steven
Wermer Paul H.
Intel Corporation
Potter Roy
Schwegman Lundberg Woessner & Kluth P.A.
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